Simulating in Cadence a D-latch cell DL8 from AMS 0.6 Hit-K

M

Mircea Gindila

Guest
Hello,

I am trying to simulate with SpectreS a D-latch cell DL8 from HRDLIB
of AMS 0.6micron hit kit. I am using Vpulse sources for the D and
Clock inputs and gndd for ground connection. I also loaded the output
with a gate. the problem is that when I run the simulations with and
digital input signal with levels from 0 and 5V a frequency 100k for D
input and a clock signal with frequency 1MHz and the same signal
levels 0 and 5V the output Q is changind only between 0 and 300mv. I
suspected is to do with the fact the internal ground of the latch cell
DL8 is called differently. I had a look in the netlist after the
simulations and it semms that the internal gnd and vdd are called
differently but then they are asigned to gnd! and vdd! in which case
it should be okay.


Any ideea of what to try to get 0 and 5V at the latch output?

Looking forwared to your reply.

Many thanks,

Mircea
 
yes it looks like there's a problem with your ground/power connections.
maybe you could post your netlist that would help.


"Mircea Gindila" <mvg00r@ecs.soton.ac.uk> wrote in message
news:6d3f9566.0404220328.47f05191@posting.google.com...
Hello,

I am trying to simulate with SpectreS a D-latch cell DL8 from HRDLIB
of AMS 0.6micron hit kit. I am using Vpulse sources for the D and
Clock inputs and gndd for ground connection. I also loaded the output
with a gate. the problem is that when I run the simulations with and
digital input signal with levels from 0 and 5V a frequency 100k for D
input and a clock signal with frequency 1MHz and the same signal
levels 0 and 5V the output Q is changind only between 0 and 300mv. I
suspected is to do with the fact the internal ground of the latch cell
DL8 is called differently. I had a look in the netlist after the
simulations and it semms that the internal gnd and vdd are called
differently but then they are asigned to gnd! and vdd! in which case
it should be okay.


Any ideea of what to try to get 0 and 5V at the latch output?

Looking forwared to your reply.

Many thanks,

Mircea
Click to expand...
 
Hi Mircea,

From a first look at your problem, it seems that something is
wrong with the power or ground connections (as Stephane stated)

You can discuss this with people at your institute, since I know
they fabricated some designs at CMP, and issued with this design-kit :
Reuben Wilcock or David Varghese

Otherwise, you may address your question to me, and I will make
the necessary support.

Regards,

================================================================
Kholdoun TORKI
http://cmp.imag.fr
================================================================

Mircea Gindila wrote:

Hello,

I am trying to simulate with SpectreS a D-latch cell DL8 from HRDLIB
of AMS 0.6micron hit kit. I am using Vpulse sources for the D and
Clock inputs and gndd for ground connection. I also loaded the output
with a gate. the problem is that when I run the simulations with and
digital input signal with levels from 0 and 5V a frequency 100k for D
input and a clock signal with frequency 1MHz and the same signal
levels 0 and 5V the output Q is changind only between 0 and 300mv. I
suspected is to do with the fact the internal ground of the latch cell
DL8 is called differently. I had a look in the netlist after the
simulations and it semms that the internal gnd and vdd are called
differently but then they are asigned to gnd! and vdd! in which case
it should be okay.


Any ideea of what to try to get 0 and 5V at the latch output?

Looking forwared to your reply.

Many thanks,

Mircea
Click to expand...
 
Do you have a 5V dc source connect to vdd! ???
"Mircea Gindila" <mvg00r@ecs.soton.ac.uk> wrote in message
news:6d3f9566.0404220328.47f05191@posting.google.com...
Hello,

I am trying to simulate with SpectreS a D-latch cell DL8 from HRDLIB
of AMS 0.6micron hit kit. I am using Vpulse sources for the D and
Clock inputs and gndd for ground connection. I also loaded the output
with a gate. the problem is that when I run the simulations with and
digital input signal with levels from 0 and 5V a frequency 100k for D
input and a clock signal with frequency 1MHz and the same signal
levels 0 and 5V the output Q is changind only between 0 and 300mv. I
suspected is to do with the fact the internal ground of the latch cell
DL8 is called differently. I had a look in the netlist after the
simulations and it semms that the internal gnd and vdd are called
differently but then they are asigned to gnd! and vdd! in which case
it should be okay.


Any ideea of what to try to get 0 and 5V at the latch output?

Looking forwared to your reply.

Many thanks,

Mircea
Click to expand...
 
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