Simulating clock drift

[bwilson79@gmail.com]

I'm trying to simulate drift between two clocks in my simulation and
seeing some behavior that I cannot explain. It is an 80MHz clock, so
the expected period is 12.5ns. However, I'm seeing a period of
12.501ns in the simulation. Please see the code snippet below:

GenDifferentClocks : if (USE_DIFFERENT_CLOCKS = TRUE) generate
constant DRIFT_RES : time := 1 ps;
subtype DelayRange is time range 0 ps to 12.5 ns;
signal t_delay : time := 0 ps;
signal clk_drifted : std_logic;
begin
process (clk)
begin
if rising_edge(clk) then
if (t_delay = DelayRange'high) then
t_delay <= DelayRange'low;
else
t_delay <= t_delay + DRIFT_RES;
end if;
end if;
end process;
clk_drifted <= transport clk after t_delay;
end generate GenDifferentClocks;

 

[bwilson79@gmail.com]

On Jul 26, 5:48 pm, "bwilso...@gmail.com" <bwilso...@gmail.com> wrote:

I'm trying to simulate drift between two clocks in my simulation and
seeing some behavior that I cannot explain. It is an 80MHz clock, so
the expected period is 12.5ns. However, I'm seeing a period of
12.501ns in the simulation. Please see the code snippet below:

GenDifferentClocks : if (USE_DIFFERENT_CLOCKS = TRUE) generate
constant DRIFT_RES : time := 1 ps;
subtype DelayRange is time range 0 ps to 12.5 ns;
signal t_delay : time := 0 ps;
signal clk_drifted : std_logic;
begin
process (clk)
begin
if rising_edge(clk) then
if (t_delay = DelayRange'high) then
t_delay <= DelayRange'low;
else
t_delay <= t_delay + DRIFT_RES;
end if;
end if;
end process;
clk_drifted <= transport clk after t_delay;
end generate GenDifferentClocks;

Nevermind... I think I figured out what was going on. =)