A
ALuPin@web.de
Guest
Hello newsgroup,
I am trying to understand the Xilinx reference design (XAPP391:
Design
of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD)).
When performing the functional simulation (which is included in the
download files) the error detection signal of the decoder becomes
active
on decoding of 10bit words 0x1C7, 0x1BE, 0x13E, 0x0BE
and 0x2BE.
The testbench provided with the design connects the encoder
and the decoder, so that only legal 10bit words get into the decoder.
8bit --> enc --> 10bit --> dec --> 8bit
I think that there is no error injection in the testbench. In the
error cases
the 8bit words presented by the decoder are OK.
So why does these errors occur ? Has someone
already used that reference design and has met
difficulties in simulation or real hardware implementation ?
Thank you.
Best regards
Andre
I am trying to understand the Xilinx reference design (XAPP391:
Design
of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD)).
When performing the functional simulation (which is included in the
download files) the error detection signal of the decoder becomes
active
on decoding of 10bit words 0x1C7, 0x1BE, 0x13E, 0x0BE
and 0x2BE.
The testbench provided with the design connects the encoder
and the decoder, so that only legal 10bit words get into the decoder.
8bit --> enc --> 10bit --> dec --> 8bit
I think that there is no error injection in the testbench. In the
error cases
the 8bit words presented by the decoder are OK.
So why does these errors occur ? Has someone
already used that reference design and has met
difficulties in simulation or real hardware implementation ?
Thank you.
Best regards
Andre