simulating 8255

[Shalini]

On Mar 3, 4:40 am, Mark McDougall <ma...@vl.com.au> wrote:

neha.k...@gmail.com wrote:
i want to simulate 8255 using vhdl.

FYI been done (a few times) before...

is there any way to configure a port as an I/P or an O/P based on
certain conditions in d architecture? how do i go abt it?
You'd have to do it using inout ports

I'd strongly suggest you don't use inout ports in your 8255 model, but
rather use input, output and output-enable ports for each 8255 IO port and
then connect them to bidir (inout) pins on the FPGA in the top level.

so:

entity 8255 is
(
  ...
  8255_port_i    : in std_logic;
  8255_port_o    : out std_logic;
  8255_port_oe   : out std_logic;
  ...
);

8255_port_i <= fpga_birdir_port;
fpga_bidir_port <= 8255_port_o when 8255_port_oe = '1' else 'Z';

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

thanks Mark
thanks neha

 

[Shalini Keshavamurthy]

hi,
i want to simulate 8255 using vhdl.
is there any way to configure a port as an I/P or an O/P based on
certain conditions in d architecture? how do i go abt it?

 

On Mar 2, 10:56 pm, Shalini Keshavamurthy <shal233s...@gmail.com>
wrote:

hi,
i want to simulate 8255 using vhdl.
is there any way to configure a port as an I/P or an O/P based on
certain conditions in d architecture? how do i go abt it?

You'd have to do it using inout ports

 

[Mark McDougall]

neha.k.ee@gmail.com wrote:

i want to simulate 8255 using vhdl.

FYI been done (a few times) before...

is there any way to configure a port as an I/P or an O/P based on
certain conditions in d architecture? how do i go abt it?
You'd have to do it using inout ports

I'd strongly suggest you don't use inout ports in your 8255 model, but
rather use input, output and output-enable ports for each 8255 IO port and
then connect them to bidir (inout) pins on the FPGA in the top level.

so:

entity 8255 is
(
...
8255_port_i : in std_logic;
8255_port_o : out std_logic;
8255_port_oe : out std_logic;
...
);

8255_port_i <= fpga_birdir_port;
fpga_bidir_port <= 8255_port_o when 8255_port_oe = '1' else 'Z';

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266