Simulate extracted view

[Konx]

Hi.

I have a problem in simulating the extracted view of my block.

I have a schematic, where I'm using:
- a symbol representing a verilog testbench
- a symbol representing a block called Pixel
- a symbol representing a block called Oscillator

I'm able to perform simulation with ADE L if the view that I use for
Pixel and Oscillator is the schematic view (and the simulation is
correct)

But when I switch to extracted view, for both Pixel and Oscillator,
the simulation runs, but is wrong because the Pixel now has zero
voltage on the VDD! and VSS! nets.

Any ideas?

Thanks

Francesco.

 

[Riad KACED]

Hi Francesco,

It looks like you have an inherited connection problem.
Are using implicit inherited connections and adding a netSet on your
symbols ?
BTW, Am I right in assuming that you are using AMS Designer as a
simulator as well (or maybe spectreVerilog) since you are having a
verilog bloc. This is not likely to interfere with your problem, just
for me to know which simulator you are using.
Answering above questions would be useful for the community to help
you out with this issue although the inherited connection bit would
suffice I suppose.

Looking forward for your feedback,
Cheers,
Riad.

 

[Konx]

On Aug 26, 1:53 pm, Riad KACED <riad.ka...@gmail.com> wrote:

Hi Francesco,

It looks like you have an inherited connection problem.
Are using implicit inherited connections and adding a netSet on your
symbols ?

Hi.

Thanks for the answer

Unfortunately, I'm a real newbie of design/simulation, so...well, can
you explain your question a little bit in depth?

For what I can understand, yes, I'm using implicit inherited
connections (I mean, I just create the extracted view starting with
the layout, see after) but I add no netSet to my symbol.

The original symbol (let's say, the one I used in schematic
simulation) has no explicit VDD! and VSS! pin (only pins like clock,
trigger, pixel_in etc...) but is working.

BTW, Am I right in assuming that you are using AMS Designer as a
simulator as well (or maybe spectreVerilog) since you are having a
verilog bloc. This is not likely to interfere with your problem, just
for me to know which simulator you are using.

I'm using spectreVerilog.

To explain better what I'm doing:

I have a complete layout of the Pixel block (DRC and LVS are clean, so
no errors). Then, I use Layout XL to produce a so-called av_extracted
view. What I've done is: open Layout XL then go to Assura --> Run RCX.

In this window I have many tabs: the only thing I change is in
Extraction tab, where I put my Ref Node to VSS!. (other parameters are
there as default, as, for example, the directory where the LVS run is
located, in Run details tab).

Then I click Ok, and I have the av_extracted as result. (so, in the
library manager now I have a cell that has schematic, layout,
extracted and symbol view).

In another cell I use this Pixel in a schematic, so I just change, in
the config file, the view to use from schematic to extracted (I
followed some explanation I found on the web and the cadence help,
here).

After this, I open the schematic (using the config view), set my
simulator (specteVerilog), set the libraries I have to use (the same
library I used in the simulation with the schematic view), choose the
analisys (transient) and run.

Simulator starts but, as I said, no VDD! or VSS! signals are visible
when I plot them (I use Output to Plot --> select on schematic, and
then I open the extracted view and select the ground and power nets).

Sorry for this long message, but I prefer to explain what I'm doing
because maybe I make a mistake somewhere in the process

Thanks for help

Francesco.

 

[Riad KACED]

Hi Francesco,

Thank you for your detailed explanation.
Pretty hard to debug your stuff but I'm going to give it an
attempt ...
You said that when your simulate the schematic of the Pixel then
everything's alright.
According to your description of the Pixel symbol, I conclude that you
are very likely to be simulating it at HDL level, not transistor
level. In other words, the pixel should have been tied to a verilog
view. In this case, no Power/Grounds are needed as long as the
behavior of your block is well defined. But when it comes to simulate
Physical designs, like a Post-Layout view, then you definitely need to
define the Power/Grounds and set them up to the correct voltages in
your testbench. is that any clear for you ?
In fact, if you look at your Post-Layout simulation log, you must find
that Spectre would complain about floating VDD/VSS or whatever your
pwr/gnd nets.
When you create your layout, you should have Pwr/Gnd pins, say VDD/VSS
(without the ! sign as id does not make sens to have a Global signal
in a physical layout). You the define these Power/Ground on your
symbol using a netSet on your symbol for example. Look at the
following post for more information on the inherited connection
topic:
http://groups.google.com/group/comp.cad.cadence/browse_thread/thread/8fd266550bf64d06/cf63fe5b3f4ed4d7

My advice: Compare the netlist and more importantly the simulation
logs to see whether Spectre does report any extra warnings in the case
where the simulation did not work.

waiting for your feedback !

Cheers,
Riad.

 

[Riad KACED]

Hi Francesco,

Just had a quick thought this morning ...
Assuming your Pixel schematic is made of a diode and some logic
around, just guessing ... you might give some information about this.
Assuming the logic used in the Pixel schematic is bind to verilog
views in the HED.
First thing you can do is to change the binding of your logic to
Spectre views and simulate the transistor level before stepping to the
extracted view stage. Does this make sense for you ?

BTW, the ref node VSS! you have set in the RCX is used to calculate
the values of parasitic caps to ground. I can hardly see any
interaction with you problem here.

Cheers,
Riad.

 

[Konx]

On 27 Ago, 08:25, Riad KACED <riad.ka...@gmail.com> wrote:

Hi Francesco,

Just had a quick thought this morning ...
Assuming your Pixel schematic is made of a diode and some logic
around, just guessing ... you might give some information about this.

Hi.

Thanks for your answers I'm studying the manual and I'm trying to
do new simulations with different setup...still not working, but at
least I'm exploring new way.

Anyway, let's explain better the situation.

- Pixel hierarchy: top-level is symbol, where I have all the pins
(clock, trigger, pixel_in, pixel_out, token, reset, oscillator_in,
oscillator_out, etc...). If you descend hierarchy, you can see that
Pixel is using 4 basic component: 3 counters (called fast, tot, slow)
and a controller. The 3 counters have only schematic view (let's say:
the designer made the counters using flip-flop, MUX, NAND and so on
using component from a digital library). The controller has been
written using verilog, then extractin the netlist from the verilog
code. All this stuff is connected together.

- In the pixel_testebench_schematic I use 3 block: the symbol of the
Pixel, the symbol of the oscillator (oscillator is provided as it is
by another designer), the symbol of testbench and obviously there are
global power and ground (we have 2 power: VDD! and VDD1!...VDD1! is
for oscillator, VDD! for Pixel). The testbench is written in verilog.

So, if I understand correctly, I don't think that Pixel is bind to
verilog view, but it is bind to schematic view (because all Pixel
components are using schematic view).

According to your description of the Pixel symbol, I conclude that you
are very likely to be simulating it at HDL level, not transistor
level. In other words, the pixel should have been tied to a verilog
view. In this case, no Power/Grounds are needed as long as the
behavior of your block is well defined. But when it comes to simulate
Physical designs, like a Post-Layout view, then you definitely need to
define the Power/Grounds and set them up to the correct voltages in
your testbench. is that any clear for you ?

Well, more or less, I would say that is clear. In fact, during the
simulation with the schematic view I have not power or ground
connections coming out from Pixel symbol (I have clock, trigger,
etc...pins, but not VDD pins).

When I use extracted view I need this pin.

When you create your layout, you should have Pwr/Gnd pins, say VDD/VSS
(without the ! sign as id does not make sens to have a Global signal
in a physical layout). You the define these Power/Ground on your
symbol using a netSet on your symbol for example.

I created this pins in layout view, but when I create the extracted
view I can't see them anymore. (weird)

Then I define the netSet properties, but still, simulation doesn't
work.(again, weird)

Anyway, this post is just to give you a small feedback, because given
that I'm a newbie of Cadence I need more time to study how things work
and understand in a better way your advices

Really, really, thanks for your help, I'll study the manual and make
some try with these new hints!

Francesco.

 

[Riad KACED]

Hi Francesco,

Your detailed explanation confirms my thoughts, i.e your are not
simulating your design at transistor level. Having your Pixel as a
schematic does not mean anything, what really matters is the what the
leaf cells are bind to in the HED. Assuming the right switch/stop view
lists from the spectreVerilog template, I bet none of your leaf cells
is bind to a Spectre view. At this stage, I would encourage you
looking at how to work with inherited connections. You have to set the
right property name/value when your define the netSet in order to get
the connectivity well propagated.

Just out of interest, can you look at:
1. Whether you have got schematic views for your digital cells, say
the NAND.
2. Or whether the Spectre view has the same pins as the Symbol for
your digital cells, say the NAND. In case you have not a schematic
view, you must have a Spectre model file that includes your digital
libraries, you can give a look at this file to see what PWR/GND pins
are used for say the NAND.

I leave for you as per now, I'm pretty much sure you'll be able to
sort yourself out

Cheers,
Riad.