Guest
Hi,
I found it useful to be able to control my IPbus ( https://svnweb.cern.ch/trac/cactus ) connected logic from an AXI4 master.
It may be used e.g. for testing or for porting the design to the ARM equipped FPGA (Zynq of Cyclone 5?). Of course in the latter case the next step should be writing an IPbus Control Hub for ARM, working as the AXI master...
At the moment I have written a very simple bridge, allowing you to control your IPbus compatible logic from an AXI master.
As AXI uses the byte addresses and IPbus uses word addresses, the AXI address is shifted right by 2 bits (divided by 4).
As IPbus does not support single byte accesses, the bridge allows only accesses to the whole word (you'll get bus error if you try to access a single byte, two or three bytes in the word).
This implementation wraps your IPbus controlled logic as "slaves" entity.
Of course if it has additional ports except of the IPbus, you must add necessary ports in the axil2ipb entity and connect them.
This is a first attempt to write such a bridge. It has not been tested very thoroughly, so don't be surprised if something works incorrectly.
You use it on your own risk!
This is a PUBLIC DOMAIN code (according to Creative Commons CC0 license) so it is published without any warranty.
(Anyway I hope, that somebody may found it useful).
The sources may be found at https://svnweb.cern.ch/trac/cactus/ticket/1876
or on the alt.sources group: https://groups.google.com/forum/#!topic/alt.sources/b2DpVU4A5Yo
With best regards,
Wojtek
I found it useful to be able to control my IPbus ( https://svnweb.cern.ch/trac/cactus ) connected logic from an AXI4 master.
It may be used e.g. for testing or for porting the design to the ARM equipped FPGA (Zynq of Cyclone 5?). Of course in the latter case the next step should be writing an IPbus Control Hub for ARM, working as the AXI master...
At the moment I have written a very simple bridge, allowing you to control your IPbus compatible logic from an AXI master.
As AXI uses the byte addresses and IPbus uses word addresses, the AXI address is shifted right by 2 bits (divided by 4).
As IPbus does not support single byte accesses, the bridge allows only accesses to the whole word (you'll get bus error if you try to access a single byte, two or three bytes in the word).
This implementation wraps your IPbus controlled logic as "slaves" entity.
Of course if it has additional ports except of the IPbus, you must add necessary ports in the axil2ipb entity and connect them.
This is a first attempt to write such a bridge. It has not been tested very thoroughly, so don't be surprised if something works incorrectly.
You use it on your own risk!
This is a PUBLIC DOMAIN code (according to Creative Commons CC0 license) so it is published without any warranty.
(Anyway I hope, that somebody may found it useful).
The sources may be found at https://svnweb.cern.ch/trac/cactus/ticket/1876
or on the alt.sources group: https://groups.google.com/forum/#!topic/alt.sources/b2DpVU4A5Yo
With best regards,
Wojtek