Simple When problem

Hiya,

Im relativly new to VHDL but im learning by tinkering on a Digilent
Spartan 3 board, so far i've been progressing reasonably well
considering im teaching my self , but i've come unstuck with the
"when" statement.

The error I reciever is - Line 29. parse error, unexpected WHEN,
expecting SEMICOLON

But I can't see whats wrong with it, I've been reading The VHDL
cookbook and all the examples in this book and other resources seems to
suggest im synatically (spelt correctly?) correct.

My code is below if anyone would care to tell me whats incorrect with
it, its supposeed to just change the value on a seven segment display
at a clock pulse - im not interested if my numbers will count up
incorrectly and I know that the clock pulse will probably be to fast,
but i'd like to figure this out for myself at a later date.

Your Gratefully

David

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clocks is
Port ( CLK : in std_logic;
SEG : out bit_vector (6 downto 0)
);

end clocks;

architecture Behavioral of clocks is
begin
process(CLK)

variable temp: integer:=0;

begin
if CLK = '1' and CLK'event then
temp := temp + 1;

if temp >= 10 then
temp := 0;
end if;



SEG <= "0110000" when temp = 1 else --line29
"1111001" when temp = 2 else
"0110011" when temp = 3 else
"0110011" when temp = 4 else
"1011011" when temp = 5 else
"1011111" when temp = 6 else
"1110000" when temp = 7 else
"1111111" when temp = 8 else
"1110011";


end if;
end process;

end Behavioral;

 

[Jim Lewis]

googlinggoogler,
Currently conditional signal assignment is not permitted
in sequential code (a process). Instead you must use either
an if statement (similar to what you did) or a case (what
I would recommend coding). This means you will be
coding the "Seg <=" parts many times.

Also did you intend for 9 and 0 to get the same display
value.

On a standards note, it is likely that this restriction
will be removed in the next revision of the language.
Even then, I would use selected signal assignment instead.

Regards,
Jim

P.S.
A few extra comments.

1) Instead of std_logic_arith, use package numeric_std.

Hiya,

Im relativly new to VHDL but im learning by tinkering on a Digilent
Spartan 3 board, so far i've been progressing reasonably well
considering im teaching my self , but i've come unstuck with the
"when" statement.

The error I reciever is - Line 29. parse error, unexpected WHEN,
expecting SEMICOLON

But I can't see whats wrong with it, I've been reading The VHDL
cookbook and all the examples in this book and other resources seems to
suggest im synatically (spelt correctly?) correct.

My code is below if anyone would care to tell me whats incorrect with
it, its supposeed to just change the value on a seven segment display
at a clock pulse - im not interested if my numbers will count up
incorrectly and I know that the clock pulse will probably be to fast,
but i'd like to figure this out for myself at a later date.

Your Gratefully

David

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clocks is
Port ( CLK : in std_logic;
SEG : out bit_vector (6 downto 0)
);

end clocks;

architecture Behavioral of clocks is
begin
process(CLK)

variable temp: integer:=0;

begin
if CLK = '1' and CLK'event then
temp := temp + 1;

if temp >= 10 then
temp := 0;
end if;



SEG <= "0110000" when temp = 1 else --line29
"1111001" when temp = 2 else
"0110011" when temp = 3 else
"0110011" when temp = 4 else
"1011011" when temp = 5 else
"1011111" when temp = 6 else
"1110000" when temp = 7 else
"1111111" when temp = 8 else
"1110011";


end if;
end process;

end Behavioral;

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[aaaaaa]

Hi Dear,
You can't write the WHEN ELSE statement in a process.
Kindly try it outside the process or use "if" statement.
Regards