Simple verilog question

[Steve Glow]

I'm fairly new to verilog and have a very simple question which none of
my verilog books have answered:

What happens when the same register is assigned twice (using
non-blocking assignments) with different values? For example:

always @(posedge some_clock) begin

// Set the default value for the register
somereg <= 0;

// Override this later if some condition is true
if( something )
somereg <= 1;

end


Does the register end up with the first or second assignment?

Is this even considered a legal assignment, or is it undefined?

If it is legal, is this considered 'bad form' by more experienced
verilog designers?

Thanks,

Steve

 

[m]

On Mon, 03 Jan 2005 10:43:14 -0800, Jason Zheng <jzheng@jpl.nasa.gov>
wrote:

mk wrote:
On Mon, 03 Jan 2005 10:49:16 -0500, Steve Glow <sag@ollies.net> wrote:


I'm fairly new to verilog and have a very simple question which none of
my verilog books have answered:

What happens when the same register is assigned twice (using
non-blocking assignments) with different values? For example:

always @(posedge some_clock) begin

// Set the default value for the register
somereg <= 0;

// Override this later if some condition is true
if( something )
somereg <= 1;

end


Does the register end up with the first or second assignment?

Is this even considered a legal assignment, or is it undefined?

If it is legal, is this considered 'bad form' by more experienced
verilog designers?

Thanks,

Steve


It is legal assignment. The order of non-blocking assigments in the
same block is preserved so this will work the way you would expect. I
don't think there is anything wrong with this style.

I think you really want to use the blocking assignment here. Using the
non-blocking assignments this way would cause "somereg" to get
undeterministic result.

Do you have any reference you can cite for this claim ? The 1364 says:
"The order of the execution of distinct nonblocking assignments to a
given variable shall be preserved. This means that if there is clear
ordering of the execution of a set of nonblocking assigments, then the
order of the resulting updates of the destination of the nonblocking
assignments shall be the same as the ordering of the execution."

Think about this piece of code:
codeA
always @ (posedge clk) begin
somereg <= 1'b0;
somereg <= 1'b1;
end
/codeA

and this:

codeB
always @ (posedge clk) begin
somereg = 1'b0;
somereg = 1'b1;
end
/codeB

clearly the second code piece a lot more clear about what you want to
assign to "somereg."

I think in this case clarity is in the eye of the beholder. If you use
blocking assignments you can't infer other registers correctly in this
block i.e.:
always @ (posedge clk) begin
somereg = 1'b0;
dlysomereg <= somereg;
somereg = 1'b1;
end

If you really want to use blocking assignments, the best option is to
use a combinational second always block.

The first piece basically states that there are two
active drivers for "somereg," one being 0 and the other being 1.

Not really. There is only one driver here. I think you are confusing
this case with the one where there are two separate always blocks and
assignments are done concurrently from different always blocks. In
that case even blocking assignments wouldn't save you.

Also, it won't hurt to actually try it out yourself with a piece of test code.
I definitely concur but there is always the possibility that you'll be

writing to the implementation (which can be broken) as opposed to the
standard (which may be broken too but at least it's in writing

 

[m]

On Mon, 03 Jan 2005 10:49:16 -0500, Steve Glow <sag@ollies.net> wrote:

I'm fairly new to verilog and have a very simple question which none of
my verilog books have answered:

What happens when the same register is assigned twice (using
non-blocking assignments) with different values? For example:

always @(posedge some_clock) begin

// Set the default value for the register
somereg <= 0;

// Override this later if some condition is true
if( something )
somereg <= 1;

end


Does the register end up with the first or second assignment?

Is this even considered a legal assignment, or is it undefined?

If it is legal, is this considered 'bad form' by more experienced
verilog designers?

Thanks,

Steve

It is legal assignment. The order of non-blocking assigments in the
same block is preserved so this will work the way you would expect. I
don't think there is anything wrong with this style.

 

[Jason Zheng]

mk wrote:

On Mon, 03 Jan 2005 10:49:16 -0500, Steve Glow <sag@ollies.net> wrote:


I'm fairly new to verilog and have a very simple question which none of
my verilog books have answered:

What happens when the same register is assigned twice (using
non-blocking assignments) with different values? For example:

always @(posedge some_clock) begin

// Set the default value for the register
somereg <= 0;

// Override this later if some condition is true
if( something )
somereg <= 1;

end


Does the register end up with the first or second assignment?

Is this even considered a legal assignment, or is it undefined?

If it is legal, is this considered 'bad form' by more experienced
verilog designers?

Thanks,

Steve


It is legal assignment. The order of non-blocking assigments in the
same block is preserved so this will work the way you would expect. I
don't think there is anything wrong with this style.

I think you really want to use the blocking assignment here. Using the
non-blocking assignments this way would cause "somereg" to get
undeterministic result. Think about this piece of code:

<codeA>
always @ (posedge clk) begin
somereg <= 1'b0;
somereg <= 1'b1;
end
</codeA>

and this:

<codeB>
always @ (posedge clk) begin
somereg = 1'b0;
somereg = 1'b1;
end
</codeB>

clearly the second code piece a lot more clear about what you want to
assign to "somereg." The first piece basically states that there are two
active drivers for "somereg," one being 0 and the other being 1. Also,
it won't hurt to actually try it out yourself with a piece of test code.

 

[Jan Decaluwe]

Jason Zheng wrote:

mk wrote:

On Mon, 03 Jan 2005 10:49:16 -0500, Steve Glow <sag@ollies.net> wrote:


I'm fairly new to verilog and have a very simple question which none of
my verilog books have answered:

What happens when the same register is assigned twice (using
non-blocking assignments) with different values? For example:

always @(posedge some_clock) begin

// Set the default value for the register
somereg <= 0;

// Override this later if some condition is true
if( something )
somereg <= 1;

end


Does the register end up with the first or second assignment?

Is this even considered a legal assignment, or is it undefined?

If it is legal, is this considered 'bad form' by more experienced
verilog designers?

Thanks,

Steve



It is legal assignment. The order of non-blocking assigments in the
same block is preserved so this will work the way you would expect. I
don't think there is anything wrong with this style.


I think you really want to use the blocking assignment here. Using the
non-blocking assignments this way would cause "somereg" to get
undeterministic result. Think about this piece of code:

codeA
always @ (posedge clk) begin
somereg <= 1'b0;
somereg <= 1'b1;
end
/codeA

and this:

codeB
always @ (posedge clk) begin
somereg = 1'b0;
somereg = 1'b1;
end
/codeB

clearly the second code piece a lot more clear about what you want to
assign to "somereg." The first piece basically states that there are two
active drivers for "somereg," one being 0 and the other being 1. Also,
it won't hurt to actually try it out yourself with a piece of test code.

You really should take your own advice - which should
convince you that what you are saying is not true.
In fact, default value assigments (which per definition can only
be done in sequential code) are a great coding style,
both for blocking and for non-blocking assignments.

Jan

--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Using Python as a hardware description language:
http://jandecaluwe.com/Tools/MyHDL/Overview.html

 

[Jason Zheng]

Jan Decaluwe wrote:

Jason Zheng wrote:

mk wrote:

On Mon, 03 Jan 2005 10:49:16 -0500, Steve Glow <sag@ollies.net> wrote:


I'm fairly new to verilog and have a very simple question which none of
my verilog books have answered:

What happens when the same register is assigned twice (using
non-blocking assignments) with different values? For example:

always @(posedge some_clock) begin
// Set the default value for the register
somereg <= 0;

// Override this later if some condition is true
if( something )
somereg <= 1;

end


Does the register end up with the first or second assignment?

Is this even considered a legal assignment, or is it undefined?

If it is legal, is this considered 'bad form' by more experienced
verilog designers?

Thanks,

Steve




It is legal assignment. The order of non-blocking assigments in the
same block is preserved so this will work the way you would expect. I
don't think there is anything wrong with this style.



I think you really want to use the blocking assignment here. Using the
non-blocking assignments this way would cause "somereg" to get
undeterministic result. Think about this piece of code:

codeA
always @ (posedge clk) begin
somereg <= 1'b0;
somereg <= 1'b1;
end
/codeA

and this:

codeB
always @ (posedge clk) begin
somereg = 1'b0;
somereg = 1'b1;
end
/codeB

clearly the second code piece a lot more clear about what you want to
assign to "somereg." The first piece basically states that there are
two active drivers for "somereg," one being 0 and the other being 1.
Also, it won't hurt to actually try it out yourself with a piece of
test code.


You really should take your own advice - which should
convince you that what you are saying is not true.
In fact, default value assigments (which per definition can only
be done in sequential code) are a great coding style,
both for blocking and for non-blocking assignments.

Jan

--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Using Python as a hardware description language:
http://jandecaluwe.com/Tools/MyHDL/Overview.html
Yah, I should've tested it myself. Sorry about that.