Simple Verilog Q

[Greg]

module div_16M(clk,tc_1s);

input clk;
output tc_1s;

reg[23:0] count;
reg tc_1s;

always@ (posedge clk);
begin
count <= count + 1;
tc_1s <= &count;
end


Doesn't this module just output(tc_1s) a 0 until the count reaches all
1s in which then it outputs(tc_1s) a 1?

 

[Allan Herriman]

On 24 Nov 2004 20:40:03 -0800, gsletch@yahoo.com (Greg) wrote:

module div_16M(clk,tc_1s);

input clk;
output tc_1s;

reg[23:0] count;
reg tc_1s;

always@ (posedge clk);
begin
count <= count + 1;
tc_1s <= &count;
end


Doesn't this module just output(tc_1s) a 0 until the count reaches all
1s in which then it outputs(tc_1s) a 1?

In synthesis, it will do as you suggest.
In simulation, it will output an X forever.

Consider adding something that will give 'count' an initial value.
This could be as simple as initialising it where it is declared, e.g.

reg [23:0] count = 0;

or perhaps you could code an async or sync reset into the always
block.

Regards,
Allan

 

[John Penton]

Greg wrote:

module div_16M(clk,tc_1s);

input clk;
output tc_1s;

reg[23:0] count;
reg tc_1s;

always@ (posedge clk);
begin
count <= count + 1;
tc_1s <= &count;
end


Doesn't this module just output(tc_1s) a 0 until the count reaches all
1s in which then it outputs(tc_1s) a 1?

Not quite - even once you have initialised "count" as Allan suggests, the
tc_1s signal will be a cycle later than you expect - in other words it will
be asserted when count == 0 (having wrapped round). The reason for this is
you have used non-blocking assignments "<=", so "tc_1s <= &count;" does not
happen after "count <= count + 1;". Both statements use the previous
version of "count" when calculating new values.

John

--
John Penton - posting as an individual unless otherwise indicated.

 

[john jakson]

"John Penton" <John.Penton@arm.com> wrote in message news:<co4i9u$krf$1@cam-news1.cambridge.arm.com>...

Greg wrote:
module div_16M(clk,tc_1s);

input clk;
output tc_1s;

reg[23:0] count;
reg tc_1s;

always@ (posedge clk);
begin
count <= count + 1;
tc_1s <= &count;
end


Doesn't this module just output(tc_1s) a 0 until the count reaches all
1s in which then it outputs(tc_1s) a 1?

Not quite - even once you have initialised "count" as Allan suggests, the
tc_1s signal will be a cycle later than you expect - in other words it will
be asserted when count == 0 (having wrapped round). The reason for this is
you have used non-blocking assignments "<=", so "tc_1s <= &count;" does not
happen after "count <= count + 1;". Both statements use the previous
version of "count" when calculating new values.

John

If you want tc_ts 1 when count is all 1s, just change & into ==
0xfffffe pattern match since & was already == 0xffffff equivalent. Not
exactly great coding though (and fix the syntax).

regards

johnjakson_usa_com

 

[Allan Herriman]

On 3 Dec 2004 05:52:41 -0800, johnjakson@yahoo.com (john jakson)
wrote:

"John Penton" <John.Penton@arm.com> wrote in message news:<co4i9u$krf$1@cam-news1.cambridge.arm.com>...
Greg wrote:
module div_16M(clk,tc_1s);

input clk;
output tc_1s;

reg[23:0] count;
reg tc_1s;

always@ (posedge clk);
begin
count <= count + 1;
tc_1s <= &count;
end


Doesn't this module just output(tc_1s) a 0 until the count reaches all
1s in which then it outputs(tc_1s) a 1?

Not quite - even once you have initialised "count" as Allan suggests, the
tc_1s signal will be a cycle later than you expect - in other words it will
be asserted when count == 0 (having wrapped round). The reason for this is
you have used non-blocking assignments "<=", so "tc_1s <= &count;" does not
happen after "count <= count + 1;". Both statements use the previous
version of "count" when calculating new values.

John


If you want tc_ts 1 when count is all 1s, just change & into ==
0xfffffe pattern match since & was already == 0xffffff equivalent. Not
exactly great coding though (and fix the syntax).

'count' is an internal register in the OP's example (i.e. it doesn't
affect any output port apart from tc_ls), so the phase of count with
respect to tc_ls really doesn't matter.

Regards,
Allan