Simple Verilog Example and X value

C

czeczek

Guest
Hi,

I've got following simple verilog example simulated in ModelSim (each
module in seperate file).
Module m16 - counter counts clock and exposing counter value to the
output. Module binToSeg gets this value thru wires w3 to w0 in top
module board and performs additional tasks.
Problem is that wires w3 to w0 are always in state X but m16 output
(ctr) is always determined during simulation.

Does anyone have an idea what I'm doing wrong ? I'd be appreciated for
any suggestions.

Thanks,
Marcin

----------------------------------- example
--------------------------------------
module m16
(output reg [3:0] ctr = 1,
input clock);

always @(posedge clock)
ctr <= ctr + 1;

endmodule

module m555
(output reg clock);

initial
#5 clock = 1;

always
#50 clock = ~clock;

endmodule

module binToSeg
(output eSeg,
input p1, p2, p3, p4);

nand #1
g1 (p1, C, ~D),
g2 (p2, A, B),
g3 (p3, ~B, ~D),
g4 (p4, A, C),
g5 (eSeg, p1, p2, p3, p4);

endmodule

module board;
wire clock, eSeg, w3, w2, w1, w0;

m555 clockGen (clock);
m16 counter ({w3, w2, w1, w0}, clock);
binToSeg disp (eSeg, w3, w2, w1, w0);

initial
$monitor ($time,,,"count=%d, eSeg=%d", {w3, w2, w1, w0}, eSeg);

endmodule
 
I don't think it is legal to have an initializer inside an ANSI-style
output port declaration. However, I would have expected the tool to
give you a syntax error instead of behaving strangely.

czeczek wrote:
Hi,

I've got following simple verilog example simulated in ModelSim (each
module in seperate file).
Module m16 - counter counts clock and exposing counter value to the
output. Module binToSeg gets this value thru wires w3 to w0 in top
module board and performs additional tasks.
Problem is that wires w3 to w0 are always in state X but m16 output
(ctr) is always determined during simulation.

Does anyone have an idea what I'm doing wrong ? I'd be appreciated for
any suggestions.

Thanks,
Marcin

----------------------------------- example
--------------------------------------
module m16
(output reg [3:0] ctr = 1,
input clock);

always @(posedge clock)
ctr <= ctr + 1;

endmodule

module m555
(output reg clock);

initial
#5 clock = 1;

always
#50 clock = ~clock;

endmodule

module binToSeg
(output eSeg,
input p1, p2, p3, p4);

nand #1
g1 (p1, C, ~D),
g2 (p2, A, B),
g3 (p3, ~B, ~D),
g4 (p4, A, C),
g5 (eSeg, p1, p2, p3, p4);

endmodule

module board;
wire clock, eSeg, w3, w2, w1, w0;

m555 clockGen (clock);
m16 counter ({w3, w2, w1, w0}, clock);
binToSeg disp (eSeg, w3, w2, w1, w0);

initial
$monitor ($time,,,"count=%d, eSeg=%d", {w3, w2, w1, w0}, eSeg);

endmodule
Click to expand...
 
Hi Czeczek,
Change the following module to
module binToSeg
(output eSeg,
input A, B, C, D);


nand #1
g1 (p1, C, ~D),
g2 (p2, A, B),
g3 (p3, ~B, ~D),
g4 (p4, A, C),
g5 (eSeg, p1, p2, p3, p4);


endmodule
The reason is A,B,C,D is floating wire which will result in p1,p2,p3,p4
remain X.Contention is the reason.

Best regards,
ABC



czeczek wrote:
Hi,

I've got following simple verilog example simulated in ModelSim (each
module in seperate file).
Module m16 - counter counts clock and exposing counter value to the
output. Module binToSeg gets this value thru wires w3 to w0 in top
module board and performs additional tasks.
Problem is that wires w3 to w0 are always in state X but m16 output
(ctr) is always determined during simulation.

Does anyone have an idea what I'm doing wrong ? I'd be appreciated for
any suggestions.

Thanks,
Marcin

----------------------------------- example
--------------------------------------
module m16
(output reg [3:0] ctr = 1,
input clock);

always @(posedge clock)
ctr <= ctr + 1;

endmodule

module m555
(output reg clock);

initial
#5 clock = 1;

always
#50 clock = ~clock;

endmodule

module binToSeg
(output eSeg,
input p1, p2, p3, p4);

nand #1
g1 (p1, C, ~D),
g2 (p2, A, B),
g3 (p3, ~B, ~D),
g4 (p4, A, C),
g5 (eSeg, p1, p2, p3, p4);

endmodule

module board;
wire clock, eSeg, w3, w2, w1, w0;

m555 clockGen (clock);
m16 counter ({w3, w2, w1, w0}, clock);
binToSeg disp (eSeg, w3, w2, w1, w0);

initial
$monitor ($time,,,"count=%d, eSeg=%d", {w3, w2, w1, w0}, eSeg);

endmodule
Click to expand...
 
Hi ABC,

Of course, it's just escaped my attention that's silly bug.

Thanks !!

ABC napisal(a):
Hi Czeczek,
Change the following module to
module binToSeg
(output eSeg,
input A, B, C, D);


nand #1
g1 (p1, C, ~D),
g2 (p2, A, B),
g3 (p3, ~B, ~D),
g4 (p4, A, C),
g5 (eSeg, p1, p2, p3, p4);


endmodule
The reason is A,B,C,D is floating wire which will result in p1,p2,p3,p4
remain X.Contention is the reason.

Best regards,
ABC



czeczek wrote:
Hi,

I've got following simple verilog example simulated in ModelSim (each
module in seperate file).
Module m16 - counter counts clock and exposing counter value to the
output. Module binToSeg gets this value thru wires w3 to w0 in top
module board and performs additional tasks.
Problem is that wires w3 to w0 are always in state X but m16 output
(ctr) is always determined during simulation.

Does anyone have an idea what I'm doing wrong ? I'd be appreciated for
any suggestions.

Thanks,
Marcin

----------------------------------- example
--------------------------------------
module m16
(output reg [3:0] ctr = 1,
input clock);

always @(posedge clock)
ctr <= ctr + 1;

endmodule

module m555
(output reg clock);

initial
#5 clock = 1;

always
#50 clock = ~clock;

endmodule

module binToSeg
(output eSeg,
input p1, p2, p3, p4);

nand #1
g1 (p1, C, ~D),
g2 (p2, A, B),
g3 (p3, ~B, ~D),
g4 (p4, A, C),
g5 (eSeg, p1, p2, p3, p4);

endmodule

module board;
wire clock, eSeg, w3, w2, w1, w0;

m555 clockGen (clock);
m16 counter ({w3, w2, w1, w0}, clock);
binToSeg disp (eSeg, w3, w2, w1, w0);

initial
$monitor ($time,,,"count=%d, eSeg=%d", {w3, w2, w1, w0}, eSeg);

endmodule
Click to expand...
 
zeczek wrote:

Problem is that wires w3 to w0 are always in state X but m16 output
(ctr) is always determined during simulation.
Click to expand...

module m16
(output reg [3:0] ctr = 1,
input clock);

always @(posedge clock)
ctr <= ctr + 1;

endmodule
Click to expand...
Use a reset instead of initializing the counter variable ctr.

Let me add: Initial values are not synthesizable.

Ralf
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top