Simple transmission

Hi

Im trying to send a byte via RS output (txd line)
my code :
....
process(SCL)

begin

ADCAdressWR <= "00010011"; --byte to send
if rising_edge(SCL) then

for i in 0 to 7 loop
txd <= ADCAdressWR(i);
end loop;
end if;
On terminal i can see only 00.

Im newbie to VHDL, so i'm asking for i little help
thx in advance

 

[Symon]

<wojjed@gmail.com> wrote in message
news:d7f4b997-b7d5-4ce9-a91b-bd1ada70cf3e@i12g2000prf.googlegroups.com...

Hi

Im trying to send a byte via RS output (txd line)
my code :
...
process(SCL)

begin

ADCAdressWR <= "00010011"; --byte to send
if rising_edge(SCL) then

for i in 0 to 7 loop
txd <= ADCAdressWR(i);
end loop;
end if;
On terminal i can see only 00.

Im newbie to VHDL, so i'm asking for i little help
thx in advance

GIYF
vhdl shift register
HTH., Syms.

 

[sly]

wojjed@gmail.com a écrit :

Hi

Im trying to send a byte via RS output (txd line)
my code :
....
process(SCL)

begin

ADCAdressWR <= "00010011"; --byte to send
if rising_edge(SCL) then

for i in 0 to 7 loop
txd <= ADCAdressWR(i);
end loop;
end if;
On terminal i can see only 00.

Im newbie to VHDL, so i'm asking for i little help
thx in advance
your code can extended to:

ADCAdressWR <= "00010011"; --byte to send
if rising_edge(SCL) then
txd <= ADCAdressWR(0);
txd <= ADCAdressWR(1);
txd <= ADCAdressWR(2);
txd <= ADCAdressWR(3);
txd <= ADCAdressWR(4);
txd <= ADCAdressWR(5);
txd <= ADCAdressWR(6);
txd <= ADCAdressWR(7);
end if;

this simplify to:

ADCAdressWR <= "00010011"; --byte to send
if rising_edge(SCL) then
txd <= ADCAdressWR(7);
end if;

because you are in the same simulation time in the rising_edge condition.
You need to have a counter incrementing at each rising_edge of clock for
exemple or shifting ADCAdressWr at each cycle:

ADCAdressWr <= "0" & ADCAdressWr(7 downto 1);
txd<=ADCAdressWR(0);

 

On 23 Sty, 12:52, "Symon" <symon_bre...@hotmail.com> wrote:

woj...@gmail.com> wrote in message

news:d7f4b997-b7d5-4ce9-a91b-bd1ada70cf3e@i12g2000prf.googlegroups.com...





Hi

Im trying to send a byte via RS output (txd line)
my code :
...
process(SCL)

begin

ADCAdressWR <= "00010011";  --byte to send
if rising_edge(SCL) then

for i in 0 to 7 loop
txd <=  ADCAdressWR(i);
end loop;
end if;
On terminal i can see only 00.

Im newbie to VHDL, so i'm asking for i little help
thx in advance

GIYF
vhdl shift register
HTH., Syms.- Ukryj cytowany tekst -

- Pokaż cytowany tekst -

1)If I would know how to use code from google i wouldnt post a message
here.
2)I still have not found any code, which consist shift register with
parallel input and serial output.
3)Im newbie to VHDL

 

[Symon]

Dear Wojjed
Jeez, you're not looking very hard are you?
vhdl piso
Does the Gdansk University of Technology run a course on how to search
t'internet for stuff? ;-) Also, you probably should buy a textbook.
HTH., Syms.
p.s. http://rtfm.killfile.pl/

 

On 23 Sty, 14:39, "Symon" <symon_bre...@hotmail.com> wrote:

Dear Wojjed
Jeez, you're not looking very hard are you?
vhdl piso
Does the Gdansk University of Technology run a course on how to search
t'internet for stuff? ;-) Also, you probably should buy a textbook.
HTH., Syms.
p.s.http://rtfm.killfile.pl/

THX for link, its very helpful. I've already had a book.
Ps. If i am not going to explain something to somebody, i dont post a
messages like" look in google" because it is the most studpid thing on
groups which i had met so far. Most people who post on programing
groups, imho does know what are google for...