Simple synthesizable verilog question

Hello,

Are the two code snippets equivalent?

(1)

always @(posedge clk) begin
state <= 1;
if ( blah )
state <= 2;
end

(2)

always @(posedge clk) begin
if ( blah )
state <= 2;
else
state <= 1;
end

....

I ask because #1 would sometimes be better for me - set state to '1' at
the beginning, only changing it later on as required (obviously, not
'later' in real time, just later on in the code block).

Any help much appreciated

Many thanks

 

[gabor]

They are equivalent for synthesis. You will see a 0 width glitch
on state during simulation when state is not 1.

kierenj@gmail.com wrote:

Hello,

Are the two code snippets equivalent?

(1)

always @(posedge clk) begin
state <= 1;
if ( blah )
state <= 2;
end

(2)

always @(posedge clk) begin
if ( blah )
state <= 2;
else
state <= 1;
end

...

I ask because #1 would sometimes be better for me - set state to '1' at
the beginning, only changing it later on as required (obviously, not
'later' in real time, just later on in the code block).

Any help much appreciated

Many thanks

 

[gabor]

Mahurshi Akilla wrote:

is a 0 width glitch harmful in any way or is it just an indication that
something is messed up in the design and that it could be done better?

Mahurshi Akilla

gabor wrote:
They are equivalent for synthesis. You will see a 0 width glitch
on state during simulation when state is not 1.

The 0-width glitch is an artefact of simulation. There is nothing
wrong
with this style of design, and it is often used to improve readability,
especially when you have deep nested if statements and don't want
an else for each level of nesting. I only pointed out the "glitch"
because
you'll see them when you run a simulation, and for example when
browsing a waveform these glitches will sometimes be annoying
because they look like a state change when you search for the next
edge on a signal. Even in simulation, however they don't normally
affect operation because nothing will sample the glitch value.

Regards,
Gabor

 

[Chris F Clark]

Mahurshi Akilla wrote:

is a 0 width glitch harmful in any way or is it just an indication that
something is messed up in the design and that it could be done better?

Whether the 0 width glitch is harmful depends on the rest of your
design. If you treat the signal as a clock, i.e. somewhere you have
an "always @(posedge signal)", your simulator will see the glitch as
triggering an edge. That can happen, even if the signal is assigned
to some other variable (perhaps through several layers) and that is
used as a clock. Now, in practice, you are not likely to use such a
signal as a clock, and you shouldn't have edge triggered events on
garden variety (non-clock, non-reset) signals. So, the issue is
minimal.

However, the issue comes up because you want to mix combinatorial
logic and state devices. See the discussion under <= and =. There
isn't a universally accepted style that deals with all the issues. I
personally like the style where one puts the combinatorial code (using
bocking = assigns) at the beginning of the edge sensitive always block
and then cluster the assignments to state devices (using non-blocking
<= assigns) at the end of the block. Then, if the combinatorial code
gets too large or influences registers not on the same clock edge, you
can move it to a separate always @* block.

always @(posedge clock)
begin : posedge_clock
// combinatorial code
reg [7:0] for_reg1;

for_reg1 = 1; // doesn't leave the block, thus doesn't cause a glitch
if ( cond )
begin
for_reg1 = 2; // we can change the value as we see fit
end

// state devices
reg1 <= for_reg1; // now we have the final value, copy it to the real reg.
end

Now, for some people that coding style is too verbose. Be your own judge.

Hope this helps,
-Chris

*****************************************************************************
Chris Clark Internet : compres@world.std.com
Compiler Resources, Inc. Web Site : http://world.std.com/~compres
23 Bailey Rd voice : (508) 435-5016
Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours)
------------------------------------------------------------------------------

 

[Mahurshi Akilla]

is a 0 width glitch harmful in any way or is it just an indication that
something is messed up in the design and that it could be done better?

Mahurshi Akilla

gabor wrote:

They are equivalent for synthesis. You will see a 0 width glitch
on state during simulation when state is not 1.