Simple question about if statemets

G

gman

Guest
Hello All,
Assuming that all the following signal are std_logic, why isn't the
following line illegal:

if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
Term = '1' and Ready ='1') then


The compiler says:
near "and": expecting: ')'
near "or": expecting: ')'

The problem seems to go away if I pair up the operands into groups of
two using parenthesis. Why doesn't the compiler apply
order-of-operation rules and evaluate the boolean statement?

Thanks.
 
gman a écrit :
Hello All,
Assuming that all the following signal are std_logic, why isn't the
following line illegal:

if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
Term = '1' and Ready ='1') then


The compiler says:
near "and": expecting: ')'
near "or": expecting: ')'

The problem seems to go away if I pair up the operands into groups of
two using parenthesis. Why doesn't the compiler apply
order-of-operation rules and evaluate the boolean statement?
Click to expand...
Not sure for VHDL (I'am a beginer) but on most languages, both "or" and "and"
have precedence on compare operators, so your expressions would be evaluated as:

if ( PCI_Frame_n = ('0' or PCI_Trdy_n) = ( .....

You must use :
if ( (PCI_Frame_n = '0') or (PCI_Trdy_n ='0') and (Hit='1') and (Term='0') or
Click to expand...
Be careful : the "and" operator have precedence on the "or". Writen like this,
your full line will be evaluated as :

if ( (PCI_Frame_n = '0') or
((PCI_Trdy_n ='0') and (Hit='1') and (Term='0')) or
((Term = '1') and (Ready ='1')) ) then

Is it exactely that you want ?
Be precise : time taken to type some parenthesis is never loosen !

Pascal
 
I'm familiar with the order of operation rules. I'm trying to get the
boolean statement to evaluate as written i.e. the ANDs first (from left
to right) and then the ORs (from left to right). Regardless of the
order of operation, why does the compiler generate syntax errors?

Regards,

-Ali

Pascal Peyremorte wrote:
gman a écrit :
Hello All,
Assuming that all the following signal are std_logic, why isn't the
following line illegal:

if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
Term = '1' and Ready ='1') then


The compiler says:
near "and": expecting: ')'
near "or": expecting: ')'

The problem seems to go away if I pair up the operands into groups of
two using parenthesis. Why doesn't the compiler apply
order-of-operation rules and evaluate the boolean statement?

Not sure for VHDL (I'am a beginer) but on most languages, both "or" and "and"
have precedence on compare operators, so your expressions would be evaluated as:

if ( PCI_Frame_n = ('0' or PCI_Trdy_n) = ( .....

You must use :
if ( (PCI_Frame_n = '0') or (PCI_Trdy_n ='0') and (Hit='1') and (Term='0') or

Be careful : the "and" operator have precedence on the "or". Writen like this,
your full line will be evaluated as :

if ( (PCI_Frame_n = '0') or
((PCI_Trdy_n ='0') and (Hit='1') and (Term='0')) or
((Term = '1') and (Ready ='1')) ) then

Is it exactely that you want ?
Be precise : time taken to type some parenthesis is never loosen !

Pascal
Click to expand...
 
gman wrote:

I'm familiar with the order of operation rules. I'm trying to get the
boolean statement to evaluate as written i.e. the ANDs first (from left
to right) and then the ORs (from left to right). Regardless of the
order of operation, why does the compiler generate syntax errors?
Click to expand...
Coming from a C background, I've noticed that VHDL compilers sometimes
require what I consider 'superfluous' bracketing as well. I've never
bothered to look into it, I just add parentheses and keep going...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
gman schrieb:


if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
Term = '1' and Ready ='1') then
Click to expand...

The compiler is as confused as me. Do you mean

if ( (PCI_Frame_n = '0' or PCI_Trdy_n ='0') and Hit='1' and Term='0' or
(Term = '1' and Ready ='1') ) then

or

if ( PCI_Frame_n = '0' or (PCI_Trdy_n ='0' and Hit='1' and Term='0') or
(Term = '1' and Ready ='1') ) then

or something else? There is no left-to-right elavuation in VHDL as in C.

Ralf
 
What I'm trying to do is this in boolean:

!PCI_Frame_n + !PCI_Trdy_n*Hit* !Term+Term*Ready


Ralf Hildebrandt wrote:
gman schrieb:


if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
Term = '1' and Ready ='1') then


The compiler is as confused as me. Do you mean

if ( (PCI_Frame_n = '0' or PCI_Trdy_n ='0') and Hit='1' and Term='0' or
(Term = '1' and Ready ='1') ) then

or

if ( PCI_Frame_n = '0' or (PCI_Trdy_n ='0' and Hit='1' and Term='0') or
(Term = '1' and Ready ='1') ) then

or something else? There is no left-to-right elavuation in VHDL as in C.

Ralf
Click to expand...
 
gman wrote:
What I'm trying to do is this in boolean:

!PCI_Frame_n + !PCI_Trdy_n*Hit* !Term+Term*Ready
Click to expand...
Just set brackets to force the evaluation to the desired operator
precedence.

Ralf
 
VHDL does not allow parallel combinations of AND and OR in expressions.
You must use parentheses to specify the operation precedence you want.

Think about it; if we had a hard time trying to figure out what you
wanted, so would some poor sap that will have to maintain your design
in the future.

AND/OR precedence errors are a common error source in most programming,
so VHDL just forces you to explicitly tell it what you want.

Andy


gman wrote:
What I'm trying to do is this in boolean:

!PCI_Frame_n + !PCI_Trdy_n*Hit* !Term+Term*Ready


Ralf Hildebrandt wrote:
gman schrieb:


if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
Term = '1' and Ready ='1') then


The compiler is as confused as me. Do you mean

if ( (PCI_Frame_n = '0' or PCI_Trdy_n ='0') and Hit='1' and Term='0' or
(Term = '1' and Ready ='1') ) then

or

if ( PCI_Frame_n = '0' or (PCI_Trdy_n ='0' and Hit='1' and Term='0') or
(Term = '1' and Ready ='1') ) then

or something else? There is no left-to-right elavuation in VHDL as in C.

Ralf
Click to expand...
 
"gman" <aghoras@gmail.com> wrote in news:1165873311.697175.252830@
79g2000cws.googlegroups.com:

Hello All,
Assuming that all the following signal are std_logic, why isn't the
following line illegal:

if ( PCI_Frame_n = '0' or PCI_Trdy_n ='0' and Hit='1' and Term='0' or
Term = '1' and Ready ='1') then


The compiler says:
near "and": expecting: ')'
near "or": expecting: ')'

The problem seems to go away if I pair up the operands into groups of
two using parenthesis. Why doesn't the compiler apply
order-of-operation rules and evaluate the boolean statement?

Thanks.
Click to expand...
It is because AND and OR are boolean operators.


if (( PCI_Frame_n = '0') or (PCI_Trdy_n ='0') and (Hit='1') and (Term='0')
or (Term = '1') and (Ready ='1')) then

should compile

--
Posted via a free Usenet account from http://www.teranews.com
 
Nope, AND and OR are defined for std_logic too. However, the result is
still a std_logic, and thus the entire expression must be compared to
'1' or '0' to return a boolean which is required in the IF condition.

if (not pci_frame_n or (not pci_trdy_n and hit and not term) or (term
and ready)) = '1' then

No final, all-enclosing parentheses are required either.

Andy

Ale Brewer wrote:
It is because AND and OR are boolean operators.


if (( PCI_Frame_n = '0') or (PCI_Trdy_n ='0') and (Hit='1') and (Term='0')
or (Term = '1') and (Ready ='1')) then

should compile

--
Posted via a free Usenet account from http://www.teranews.com
Click to expand...
 
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