"simple" problem

[Simone Winkler]

Hello!

I'm not programming VHDL now for a long time, so I've got a problem, that is
for sure quite simple:

I've got a vhdl source code that I took from the Xilinx Application Notes.
One of the ports is an inout that has 32 bits. Now what I want is two
16bit-ports. I JUST want to have the two 16bit ports on the entity, but it
doesn't matter if the vhdl code works with the 32bit-signal, so I just want
to put the two 16bit-signals together after declaring the entity.

so what i did was:

entity ... is
port( sys_data: inout std_logic_vector(15 downto 0);
sys_addr: inout std_logic_vector(15 downto 0);
...
);
end entity ...;

architechture behavioural of ... is

signal AD: std_logic_vector(31 downto 0);
...

component (...)
...

begin

%component instantiations%

process(...)
...
end process;

process(...)
...
end process;

AD <= sys_addr(15 downto 0) & sys_data(15 downto 0);
...

end architecture;

WHY doesn't it work?
When I do a behavioural simulation with modelsim, AD is undefined (all the
16 bits) and nearly everything else too.

Please don't *kill* me, because it's a silly question.. i just can't find a
solution!

THANX!

Simone

 

[Jonathan Bromley]

"Simone Winkler" <simone.winkler@gmx.at> wrote in
message news:1069952673.594639@news.liwest.at...

I've got a vhdl source code that I took from the Xilinx Application Notes.
One of the ports is an inout that has 32 bits. Now what I want is two
16bit-ports. I JUST want to have the two 16bit ports on the entity, but it
doesn't matter if the vhdl code works with the 32bit-signal, so I just
want
to put the two 16bit-signals together after declaring the entity.

entity ... is
port( sys_data: inout std_logic_vector(15 downto 0);
sys_addr: inout std_logic_vector(15 downto 0);
...
);
end entity ...;

architechture behavioural of ... is

signal AD: std_logic_vector(31 downto 0);
begin
[...]
AD <= sys_addr(15 downto 0) & sys_data(15 downto 0);
[...]
end architecture;

WHY doesn't it work?
When I do a behavioural simulation with modelsim, AD is undefined (all the
16 bits) and nearly everything else too.

If these were input ports, the code you post would be fine.

In the absence of anything else, the code is *still* fine
even for inout ports.

However, there could easily be some problems about the way you
are driving AD to push data onto the inout ports when your
internal outputs are enabled. Something like this:

AD <= sys_addr(15 downto 0) & sys_data(15 downto 0);
sys_addr <= AD(15 downto 0);
sys_data <= AD(15 downto 0);

Whoops, now we really have a problem - a combinational loop.

So I would have thought the easy solution was to make a
wrapper component that splits the bus for you...

entity wrapper is
port

sys_data: inout std_logic_vector(15 downto 0);
sys_addr: inout std_logic_vector(15 downto 0);
[...] -- pass all the other signals through too
);
end;

architecture W of wrapper is
component the_old_32_bit_version
port (
AD: inout std_logic_vector(31 downto 0);
[...] -- other stuff
);
end component;
begin
guts: AD port map (
AD(15 downto 0) => sys_data,
AD(31 downto 16) => sys_addr);
end;

HTH

--

Jonathan Bromley, Consultant

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