Simple problem! with component instantiation...

[Xin Xiao]

Hi! I have a simple problem!

I am generating a few registers with this code

gen : for i in num_registers - 1 downto 0 generate
reg : Register
port map ( Clk => Clk,
Load => s_Load(i),
Din => BusW,
Dout => s_Out(i));
end generate;

The problem is that signal "s_Load(i)" should be

s_Load(i) <= Another_Signal(i) and Another_Signal2;

("s_Load" and "Another_Signal" are std_logic_vector and "Another_Signal2" is
std_logic.)

If i put

gen : for i in num_registers - 1 downto 0 generate
reg : Register
port map ( Clk => Clk,
Load => Another_Signal(i) and Another_Signal2,

it gives me an error.

How can I solve this?

 

[Eli Bendersky]

On Jan 26, 5:32 am, "Xin Xiao" <x...@x.com> wrote:

Hi! I have a simple problem!

I am generating a few registers with this code

gen : for i in num_registers - 1 downto 0 generate
reg : Register
port map ( Clk => Clk,
Load => s_Load(i),
Din => BusW,
Dout => s_Out(i));
end generate;

The problem is that signal "s_Load(i)" should be

s_Load(i) <= Another_Signal(i) and Another_Signal2;

("s_Load" and "Another_Signal" are std_logic_vector and "Another_Signal2" is
std_logic.)

If i put

gen : for i in num_registers - 1 downto 0 generate
reg : Register
port map ( Clk => Clk,
Load => Another_Signal(i) and Another_Signal2,

it gives me an error.

How can I solve this?

You can't place logic functions on the right side of port assignments.
Generate separate statements that assign the values to signals and map
those signals into the ports.

Eli

 

[C.G.]

Hi,

have you tried something like below?

Regards,
Charles


gen : for i in num_registers - 1 downto 0 generate
-- Individual local signal in scope of each generate loop
signal s_load : std_logic;
begin
s_load <= another_signal(i) and another_signal2;
reg : Register
port map ( Clk => Clk,
Load => s_load,
Din => BusW,
Dout => s_Out(i));
end generate;