G
Geo
Guest
Hi, I've just started a digital electronics course where we will be
mainly working with VHDL, I've started reading a book and trying some
of the exercises. I'm just starting VHDL and got some problems with an
exercise requiring to describe a 2-to-1 multiplexer using a CASE
statement (in the sequential statements chapter).
I've already implemented the multiplexer using a when statement in the
output assignent, but failed when trying with the case statement, see:
[code:1:dc53fce723]
library ieee;
use ieee.std_logic_1164.all;
entity multiplexor is
port(
entrada0, entrada1: in std_logic;
selector: in std_logic;
salida: out std_logic
);
end multiplexor;
architecture comp_multiplexor of multiplexor is
begin
-- it works using this:
-- salida <= entrada0 when selector = '0' else entrada1;
-- but this one doesn't work:
case selector is
when '0' => entrada0;
when '1' => entrada1;
end case;
end data_flow;
[/code:1:dc53fce723]
Am I doing things correctly? The compiler tells me about an unexpected
prefix for a array/slice/ (or something like that) on the when choices
lines.
I have problems with another exercise, however I'm sure it's about the
same thing (it's a 2-4 decoder using a CASE statement too), but I'd
like to ask if it's possible to do something like this:
entity dec24 is
port( ...
input: in std_logic_vector( 1 downto 0 );
output: out std_logic_vector( 3 downto 0)
);
end dec24
architecture bhv_dec24 of dec24 is
begin
case input is
when B"00" => ...
when B"01" => ...
...
end case;
end bhv_dec24;
[/code]
My question is about the when B"00" choices, is it correct to use such
a expression here?
Also, would the next expression be ok?
output <= ( 0 => '1', others => '0' );
I would use this one, for example, in the when B"00" choice for
assigning '1' to the appropiate output bit and '0' to all of the
others.
Last, I'd like to apologize for having some none English identifiers in
the first code, I'm not a native English speaker and just copied&pasted
that one. Thanks in advance for your help.
Regards,
José Jorge Enríquez.
PS: sorry for my poor English.
mainly working with VHDL, I've started reading a book and trying some
of the exercises. I'm just starting VHDL and got some problems with an
exercise requiring to describe a 2-to-1 multiplexer using a CASE
statement (in the sequential statements chapter).
I've already implemented the multiplexer using a when statement in the
output assignent, but failed when trying with the case statement, see:
[code:1:dc53fce723]
library ieee;
use ieee.std_logic_1164.all;
entity multiplexor is
port(
entrada0, entrada1: in std_logic;
selector: in std_logic;
salida: out std_logic
);
end multiplexor;
architecture comp_multiplexor of multiplexor is
begin
-- it works using this:
-- salida <= entrada0 when selector = '0' else entrada1;
-- but this one doesn't work:
case selector is
when '0' => entrada0;
when '1' => entrada1;
end case;
end data_flow;
[/code:1:dc53fce723]
Am I doing things correctly? The compiler tells me about an unexpected
prefix for a array/slice/ (or something like that) on the when choices
lines.
I have problems with another exercise, however I'm sure it's about the
same thing (it's a 2-4 decoder using a CASE statement too), but I'd
like to ask if it's possible to do something like this:
entity dec24 is
port( ...
input: in std_logic_vector( 1 downto 0 );
output: out std_logic_vector( 3 downto 0)
);
end dec24
architecture bhv_dec24 of dec24 is
begin
case input is
when B"00" => ...
when B"01" => ...
...
end case;
end bhv_dec24;
[/code]
My question is about the when B"00" choices, is it correct to use such
a expression here?
Also, would the next expression be ok?
output <= ( 0 => '1', others => '0' );
I would use this one, for example, in the when B"00" choice for
assigning '1' to the appropiate output bit and '0' to all of the
others.
Last, I'd like to apologize for having some none English identifiers in
the first code, I'm not a native English speaker and just copied&pasted
that one. Thanks in advance for your help.
Regards,
José Jorge Enríquez.
PS: sorry for my poor English.