Simple Elementary Verilog Query

[vikramts]

Hi every1

new programmer here with lotsa stuff to learn in verilog...im starting off
with simulations in AMS...could someone explain what this testbench(its a
testbench code for a resistor that i found online) means and how one uses
it?


// Test resistor model

simulator lang=spectre

ahdl_include "resistor.vams"

Vr (v 0) vsource type=dc dc=1
Ir (i 0) isource type=dc dc=1
R1 (v 0) resistor r=10
R2 (i 0) resistor r=10

setOptions options currents=all useprobes=yes
doDC dc print=yes

If someone could explain how i simulate components like a resistor and
other electrical components,i would really appreciate it.

Thank you!

Vikram

 

[Jason Zheng]

vikramts wrote:

Hi every1

new programmer here with lotsa stuff to learn in verilog...im starting off
with simulations in AMS...could someone explain what this testbench(its a
testbench code for a resistor that i found online) means and how one uses
it?


// Test resistor model

simulator lang=spectre

ahdl_include "resistor.vams"

Vr (v 0) vsource type=dc dc=1
Ir (i 0) isource type=dc dc=1
R1 (v 0) resistor r=10
R2 (i 0) resistor r=10

setOptions options currents=all useprobes=yes
doDC dc print=yes

If someone could explain how i simulate components like a resistor and
other electrical components,i would really appreciate it.

Thank you!

Vikram


u sure that's verilog?