Simple counter in verilog (Lattice MachXO2 7000H)

Hi,

I am working on a simple multi-channel pulse counter. The pulses counted are infrequent (up to 100 kHz), and slow (at least 1 us), coming form a comparator. In total I have 20 parallel channels (identical). Every 0.5 s I read out the counters and reset them to 0 using SPI.

The counter code is simple, contained in a module:


....
reg [17:0] counter_ripple_high;

always @(posedge slow_gate, posedge reset)
begin : b1
/*synopsys resource r0:
map_to_module = "DW01_inc",
implementation = "csa",
ops = "inc1";*/
if (reset)
counter_ripple_high <= 18'b0;
else
counter_ripple_high <= counter_ripple_high + 1'b1; // synopsys label inc1
end

assign counter = counter_ripple_high;
....


Some channels (not more than 3 out of 20) count two times the input frequency. How is it possible? One channel is not counting properly at all. I would expect the latter to be obviously caused by the speed of arithmetic logic, but the former..?
I am looking forward for your opinions.

Regards,
Krzysztof

 

[GaborSzakacs]

Cross-posted.

See thread in comp.lang.verilog