Simple Combinationail Cir. In Verilog To be fed to Prime Tim

[ilteris]

Hi all,

I have a c17, combinational circuit in verilog format. I will like to
use Synopsys's Prime Time to find the critical paths. First, I am
setting the path with "set link_path {*
/usr/local/synopsys/syn/libraries/syn/class.db}", then I read in the
verilog file. Afterwards, I am linking the design. At this point, I
need to use a constraint file. It is a simple one, but I don't know it.
I really appreciate any help.

Here is the verilog format:

module c17 (x,y,A,B,C,D,E);
input A,B,C,D,E;
output x,y;
wire w1,w2,w3,w4
nand g1(w1,A,B);
nand g2(w2,B,C);
nand g3(w3,D,w2);
nand g4(w4,w2,E);
nand g5(x,w1,w3);
nand g6(y,w3,w4);
endmodule

If I can pass this step, I will be using report_timing command.

If anybody can answer this question, and live in Dallas area, I am
willing to pay him for the big thing that I am after.

My e-mail address is iderici@smu.edu

 

[Michael]

Try something like that (for combinational logic):
set inputs [get_ports [list A B C D E]]
set outputs [get_ports [list x y]]
set_max_delay -from $inputs -to $outputs 0.07
report_timing

 

[Michael]

You have to compile your design first. And be aware - you have error in
your code.

 

[Fazela]

Hi Michael,
I dont see how we could compile the design. I mean the design would be
synthesized by Design Compiler and then we feed it directly to
Primetime with the constraints. Could you please explain what this
compilation is for?

Thanks,
FV

 

[Michael]

Hi,

What library do you have?
In general, you must perform some kind of mapping to you library.

P.S. you've forgot ";" at "wire" declaration.