Simple ALU Implementation

A

andrezz

Guest
Hi guys,
I have to implement a simple ALU of a 32bit mips..I have already
implemented many submodules (adder,multipliers,shifter...) ,that I
have to instantiate in the top level module "ALU_TOP". This module
receives as input 2 op. (a , b) and a 6bit signal OPCODE on which
basis the differents modules are instantiates.

My problem is checking the signal OPCODE directly in the architecture
(not in a process , and after begin of arch.). I used that solution
because using a process returned me errors reusing the components (and
portamaps...)
But now I cannot even check the OPCODE ("If not allowed..")..(I double
checked parenthesis or typos..)...

what should I do? Do I have to use a process? But how to use different
modules within a process?

I paste the simple part of the code .. and this not work..
Code:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu_top is


Generic (N:integer:=32);

Port ( A : in STD_LOGIC_VECTOR(N-1 downto 0);
B : in STD_LOGIC_VECTOR(N-1 downto 0);
OPCODE : in STD_LOGIC_VECTOR(5 downto 0);
FUNCT : in STD_LOGIC_VECTOR(5 downto 0);
COND : out STD_LOGIC;
ALUOut : out STD_LOGIC_VECTOR(N-1 downto 0)
);
end alu_top;

architecture Behavioral of alu_top is

component multiplier_s_u is

generic(N:integer:=16);

Port ( A : in STD_LOGIC_VECTOR(N-1 downto 0);
B : in STD_LOGIC_VECTOR(N-1 downto 0);
SIGN : in STD_LOGIC;--signed/unsigned selector
M : out STD_LOGIC_VECTOR((2*N)-1 downto 0));--output da 32
bit
end component multiplier_s_u;


begin

if OPCODE="000000" then
cond<='0';

end if;

end Behavioral;

---
ERROR:HDLParsers:164 - "F:/Poli/SDSS/MyProjects/MIPS/alu_top.vhd" Line
50. parse error, unexpected IF

Thanks in advance
 
On Nov 13, 3:50 pm, andrezz <bugp...@gmail.com> wrote:
Hi guys,
I have to implement a simple ALU of a 32bit mips..I have already
implemented many submodules (adder,multipliers,shifter...) ,that I
have to instantiate in the top level module "ALU_TOP". This module
receives as input 2 op. (a , b) and a 6bit signal OPCODE on which
basis the differents modules are instantiates.

My problem is checking the signal OPCODE directly in the architecture
(not in a process , and after begin of arch.). I used that solution
because using a process returned me errors reusing the components (and
portamaps...)
But now I cannot even check the OPCODE ("If not allowed..")..(I double
checked parenthesis or typos..)...

what should I do? Do I have to use a process? But how to use different
modules within a process?

I paste the simple part of the code .. and this not work..
Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu_top is

        Generic (N:integer:=32);

    Port ( A : in  STD_LOGIC_VECTOR(N-1 downto 0);
           B : in  STD_LOGIC_VECTOR(N-1 downto 0);
           OPCODE : in  STD_LOGIC_VECTOR(5 downto 0);
           FUNCT : in  STD_LOGIC_VECTOR(5 downto 0);
           COND : out  STD_LOGIC;
           ALUOut : out  STD_LOGIC_VECTOR(N-1 downto 0)
                          );
end alu_top;

architecture Behavioral of alu_top is

component multiplier_s_u is

         generic(N:integer:=16);

    Port ( A : in  STD_LOGIC_VECTOR(N-1 downto 0);
           B : in  STD_LOGIC_VECTOR(N-1 downto 0);
           SIGN : in  STD_LOGIC;--signed/unsigned selector
           M : out  STD_LOGIC_VECTOR((2*N)-1 downto 0));--output da 32
bit
end component multiplier_s_u;

begin

if OPCODE="000000"  then
cond<='0';

end if;

end Behavioral;

---
ERROR:HDLParsers:164 - "F:/Poli/SDSS/MyProjects/MIPS/alu_top.vhd" Line
50. parse error, unexpected IF

Thanks in advance
Click to expand...
The if-then-else structure must be used inside of a process. It may
not be used in the concurrent section of the architecture.

Dave
 
On Nov 13, 4:30 pm, Dave <dhsch...@gmail.com> wrote:
On Nov 13, 3:50 pm, andrezz <bugp...@gmail.com> wrote:



Hi guys,
I have to implement a simple ALU of a 32bit mips..I have already
implemented many submodules (adder,multipliers,shifter...) ,that I
have to instantiate in the top level module "ALU_TOP". This module
receives as input 2 op. (a , b) and a 6bit signal OPCODE on which
basis the differents modules are instantiates.

My problem is checking the signal OPCODE directly in the architecture
(not in a process , and after begin of arch.). I used that solution
because using a process returned me errors reusing the components (and
portamaps...)
But now I cannot even check the OPCODE ("If not allowed..")..(I double
checked parenthesis or typos..)...

what should I do? Do I have to use a process? But how to use different
modules within a process?

I paste the simple part of the code .. and this not work..
Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu_top is

        Generic (N:integer:=32);

    Port ( A : in  STD_LOGIC_VECTOR(N-1 downto 0);
           B : in  STD_LOGIC_VECTOR(N-1 downto 0);
           OPCODE : in  STD_LOGIC_VECTOR(5 downto 0);
           FUNCT : in  STD_LOGIC_VECTOR(5 downto 0);
           COND : out  STD_LOGIC;
           ALUOut : out  STD_LOGIC_VECTOR(N-1 downto 0)
                          );
end alu_top;

architecture Behavioral of alu_top is

component multiplier_s_u is

         generic(N:integer:=16);

    Port ( A : in  STD_LOGIC_VECTOR(N-1 downto 0);
           B : in  STD_LOGIC_VECTOR(N-1 downto 0);
           SIGN : in  STD_LOGIC;--signed/unsigned selector
           M : out  STD_LOGIC_VECTOR((2*N)-1 downto 0));--output da 32
bit
end component multiplier_s_u;

begin

if OPCODE="000000"  then
cond<='0';

end if;

end Behavioral;

---
ERROR:HDLParsers:164 - "F:/Poli/SDSS/MyProjects/MIPS/alu_top.vhd" Line
50. parse error, unexpected IF

Thanks in advance

The if-then-else structure must be used inside of a process. It may
not be used in the concurrent section of the architecture.

Dave
Click to expand...
If you want to do something like this outside a process, use a
concurrent signal assignment structured as a selected signal
assignment or conditional signal assignment(Google these terms). This
only lets you assign to one signal, though.

Example:

cond < '0' when OPCODE = "000000" else
'1' when OPCODE = "111111" else
'X';

or the other form is

with OPCODE select cond < '0' when "000000" ,
'1' when "11111",
'X' when others;

These are merely shorthands for writing the equivalent sequential if-
statement or case-statement inside a new process. (In VHDL, everything
you find in an architecture body is just a shorthand for either a
process or a block.)

But more fundamentally, step back a minute and get clear on the
difference between parallel and sequential descriptions VHDL. Reread
your reference book and try to see how the examples are constructed,
and where the right place is to implement the various bits. Put the
components ("old" logic) in the architecture body, and connect them
with signals. When you need to do something other than just using a
signal as a dumb connection between a few ports, use a process to
describe the "new" logic you want (like a state machine). Or for very
simple logic, just use a signal assignment. For example: chip_select
<= (addr = "0000") and ((read = '0') or (write = '0'));

- Kenn
 
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