simple adder that takes several cycles to complete addition

[Mahurshi Akilla]

i am trying to model a simple adder that takes 4 cycles to complete the
addition. i have written the following code and tested it in xilinx
with a few test vectors and so far, i got the correct results.

i am pasting the code below:

module clk_adder(a, b, cin, clk, sum, enable);
input [7:0] a;
input [7:0] b;
input cin;
input clk;
input enable;
output [8:0] sum;

reg [1:0] count;
reg [7:0] in1;
reg [7:0] in2;
reg in3;
reg [8:0] sum;


//set counter to zero at every enable
always @(posedge enable)
begin
count <= 0;
end

always @(posedge clk)
begin

// keep incrementing counter
// at every clock edge when enabled
if (enable == 1'b1)
begin
count <= count + 1;

// on the first cycle, copy the
// inputs
if (count == 2'b0)
begin
in1 <= a;
in2 <= b;
in3 <= cin;
end

// if four cycles are completed,
// spit the output
if (count == 2'b11)
begin
sum <= in1 + in2 + in3;
end
end

end

endmodule

is there anything you'd like to suggest me for improving this code? i
would like to know if i am going in the right direction here. (i
understand that i am not doing sign extention. i am just writing this
to learn the basics)


Mahurshi Akilla