Simple 8253 (beginner)

[aleksa]

This is what I have in mind:

1. Counter counts to zero, issues an IRQ, and reloads.
2. The CPU gets the IRQ and writes the new 'reload' value,
which should remove the IRQ.

signal counter, reload : STD_LOGIC_VECTOR (15 downto 0);

if falling_edge(clock) then
if counter = 0 then
counter <= reload;
irq <= '1';
else
counter <= counter - 1;
-- irq <= '0'; -- AUTO EOI
end if;
end if;

if rising_edge(write) then
reload <= dbus; -- reload value
irq <= '0'; -- acknowledge IRQ, EOI
end if;

If I use one process, webpack is giving me an error:
Multi-source in Unit <test> on signal <irq>; this signal is connected
to multiple drivers

If I use two processes: Signal irq cannot be synthesized.
Something like, irq is bound to two clocks.

AUTO EOI works (in simulation, dont even have the chip yet),
but the clock can be as low as 30Hz, which is too slow.

How should I ACK an IRQ with the CPU?

 

[Tricky]

On 30 Jul, 21:49, aleksa <aleks...@gmail.com> wrote:

This is what I have in mind:

1. Counter counts to zero, issues an IRQ, and reloads.
2. The CPU gets the IRQ and writes the new 'reload' value,
   which should remove the IRQ.

        signal counter, reload : STD_LOGIC_VECTOR (15 downto 0);

        if falling_edge(clock) then
                if counter = 0 then
                        counter <= reload;
                        irq <= '1';
                else
                        counter <= counter - 1;
--                      irq <= '0';                          -- AUTO EOI
                end if;
        end if;

        if rising_edge(write) then
                        reload <= dbus;                      -- reload value
                        irq <= '0';                          -- acknowledge IRQ, EOI
        end if;

If I use one process, webpack is giving me an error:
Multi-source in Unit <test> on signal <irq>; this signal is connected
to multiple drivers

If I use two processes: Signal irq cannot be synthesized.
Something like, irq is bound to two clocks.

AUTO EOI works (in simulation, dont even have the chip yet),
but the clock can be as low as 30Hz, which is too slow.

How should I ACK an IRQ with the CPU?

You cannot drive 1 signal from multiple sources. You will have to
create a mux process and a IRQ_select signal that connects IRQ to the
correct signal at any given time.

 

[aleksa]

On Jul 31, 12:50 pm, Tricky <Trickyh...@gmail.com> wrote:

On 30 Jul, 21:49, aleksa <aleks...@gmail.com> wrote:





This is what I have in mind:

1. Counter counts to zero, issues an IRQ, and reloads.
2. The CPU gets the IRQ and writes the new 'reload' value,
   which should remove the IRQ.

        signal counter, reload : STD_LOGIC_VECTOR (15 downto 0);

        if falling_edge(clock) then
                if counter = 0 then
                        counter <= reload;
                        irq <= '1';
                else
                        counter <= counter - 1;
--                      irq <= '0';                          -- AUTO EOI
                end if;
        end if;

        if rising_edge(write) then
                        reload <= dbus;                      -- reload value
                        irq <= '0';                          -- acknowledge IRQ, EOI
        end if;

If I use one process, webpack is giving me an error:
Multi-source in Unit <test> on signal <irq>; this signal is connected
to multiple drivers

If I use two processes: Signal irq cannot be synthesized.
Something like, irq is bound to two clocks.

AUTO EOI works (in simulation, dont even have the chip yet),
but the clock can be as low as 30Hz, which is too slow.

How should I ACK an IRQ with the CPU?

You cannot drive 1 signal from multiple sources. You will have to
create a mux process and a IRQ_select signal that connects IRQ to the
correct signal at any given time.- Hide quoted text -

- Show quoted text -

Please see comp.arch.fpga for this same subject:
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/aca69d92abb698bc?hl=en#