simInfo / viewInfo

[Sylvio Triebel]

Hello,

I need to implement a feature that seems to require some view (stopView) specific simInfo.
The symbol has e.g. a stopView "spectre", model is somewhere defined.

Now it should be possible to select via hierarchy editor a different view (e.g. schematic).

Unfortunately, the Artist netlister always considers the simInfo->spectre section, which was intended only for stopView
"spectre" and not for schematic_XX... and got conflict with termorder (inherited conn. <-> bulk pin)
So, if I try to setup a cdf->viewInfo->spectre then I have following problems:
-viewInfo seems not to be documented (not in cdsdoc/Sourcelink but found something from Agilent..)
-the Netlister considers (for Spectre) only viewInfo->termOrder and viewInfo->parameterList but no
propMapping/netlistProcedure... it automatically uses model as component name, no mapping possible...

Now I wonder, if I'm still on the right track...
Is there realy no documentation from Cadence?

At least for Mixed Signal I need rather view specific simInfo.. (selection btw. verilog/vhdl and schematic)

Thanks for ideas/recommendations

Regards,
Sylvio

 

[Andrew Beckett]

Sylvio Triebel wrote, on 09/23/08 08:43:

Hello,

I need to implement a feature that seems to require some view (stopView)
specific simInfo.
The symbol has e.g. a stopView "spectre", model is somewhere defined.

Now it should be possible to select via hierarchy editor a different
view (e.g. schematic).

Unfortunately, the Artist netlister always considers the
simInfo->spectre section, which was intended only for stopView
"spectre" and not for schematic_XX... and got conflict with termorder
(inherited conn. <-> bulk pin)
So, if I try to setup a cdf->viewInfo->spectre then I have following
problems:
-viewInfo seems not to be documented (not in cdsdoc/Sourcelink but
found something from Agilent..)
-the Netlister considers (for Spectre) only viewInfo->termOrder and
viewInfo->parameterList but no
propMapping/netlistProcedure... it automatically uses model as component
name, no mapping possible...

Now I wonder, if I'm still on the right track...
Is there realy no documentation from Cadence?

At least for Mixed Signal I need rather view specific simInfo..
(selection btw. verilog/vhdl and schematic)

Thanks for ideas/recommendations

Regards,
Sylvio

The actual format is not documented, but the API to create it is. See
(for example) almSetTerminalList() , almSetParameterList(),
almSetPropMappingList() etc

These are documented in the "Virtuoso Analog Design Environment SKILL Language
Reference Manual" (chapter 16, in IC5141), which can be found in PDF form at
<ICinstDir>/doc/skartistref/skartistref.pdf

Regards,

Andrew.