sim cycle

[John Smith]

Why executes the simulator the all processes at the start? Is there a design
which simulation produces a wrong result when the simulator missed executing the
all processes? Is there an entity/architecture pair?

Thanks

 

[KJ]

"John Smith" <john.smith@hotmail.com> wrote in message
news:437c1$46f0cecc$56656ea1$18092@news.chello.hu...

Why executes the simulator the all processes at the start?
You've got to start somewhere

Is there a design which simulation produces a wrong result when the
simulator missed executing the all processes?
Not that I'm aware of.

Is there an entity/architecture pair?
Only if you write one

KJ

 

[Paul Uiterlinden]

John Smith wrote:

Why executes the simulator the all processes at the start?

Because it is required according to the standards. All processes are
executed at simulation start until they suspend.

Is there a
design which simulation produces a wrong result when the simulator missed
executing the all processes?

In my opinion this question is irrelevant, because such a simulator would
not comply to the standards.

One could invent another execution model that would produce usable results,
but it would not be VHDL. If you would decide that processes only are
executed after an event occurs on a signal that the process is sensitive
to, what should be done with processes without any sensitivity list or wait
until/on statement? When should they start? These processes do exist: in a
testbench, for example.

Is there an entity/architecture pair?

Not for a process, if that is what you mean.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.

 

[John Smith]

Paul Uiterlinden wrote:

John Smith wrote:

Why executes the simulator the all processes at the start?

Because it is required according to the standards. All processes are
executed at simulation start until they suspend.

Is there a
design which simulation produces a wrong result when the simulator missed
executing the all processes?

In my opinion this question is irrelevant, because such a simulator would
not comply to the standards.

One could invent another execution model that would produce usable results,
but it would not be VHDL. If you would decide that processes only are
executed after an event occurs on a signal that the process is sensitive
to, what should be done with processes without any sensitivity list or wait
until/on statement? When should they start? These processes do exist: in a
testbench, for example.

Is there an entity/architecture pair?

Not for a process, if that is what you mean.

Ok you are right, the processes without sensitivity list have to run at the
start. But why have to run the processes with sensitivity list?

I know it is in the standard, I just would like to understand it.


Thanks

 

[Jonathan Bromley]

On Wed, 19 Sep 2007 17:14:03 +0200,
John Smith <john.smith@hotmail.com> wrote:

Ok you are right, the processes without sensitivity list have to run at the
start. But why have to run the processes with sensitivity list?

So that they can update their outputs to match the *initial* value
of their inputs. Initialisation of a VHDL signal (either its
default initialisation, or an explicit initialisation in its
declaration) happens *before* simulation begins, and does not
cause an event on the signal. If processes sensitive to those
signals did not run at the start, their outputs would keep
their initial values rather than the values that the process
computes from the initial values of its inputs.

Once the first set of process runs occurs, it typically
causes events on the processes' outputs and therefore
triggers another round of process execution. In this way,
the entire model network of processes and signals reaches
its correct stable initial values at time zero.

SystemVerilog has given itself some interesting problems
precisely because Verilog does NOT work in this way. When
true initialisation (before time 0) was added to SystemVerilog,
it did not play well with Verilog processes that typically have
a "sensitivity" event control at their start, and therefore
stall until there is an event on one of their inputs.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jim Lewis]

John,

Ok you are right, the processes without sensitivity list have to run at
the start. But why have to run the processes with sensitivity list?

Look at Jonathan's post for the long answer.

The short answer is processes with sensitivity lists run when
their inputs change and VHDL's view is that all inputs change
(get a new value) at the start of time.

Cheers,
Jim