Silicon Ensemble and Design Compiler Interface

[paololoceri@yahoo.it]

Hi all!
I am on the run to make a post layout optimization for one of my
designs!
I need some infos about incremental place and route using data coming
from DC.
At the moment:
1 I performed Global place&route using Timing Driven placement option
an Timing Driven routing. I also used the "Optimize by timing" options
in the menu "place Cells"
2 I exported pdef, setload, verilog and sdf file to DC
3 In DC i read all this informations and I performed a reoptimize
-in_place command!
4 What do I have to do next?????

Please can someone help me?

 

[m]

On 9 Mar 2005 08:23:19 -0800, "paololoceri@yahoo.it"
<paololoceri@yahoo.it> wrote:

Hi all!
I am on the run to make a post layout optimization for one of my
designs!
I need some infos about incremental place and route using data coming
from DC.
At the moment:
1 I performed Global place&route using Timing Driven placement option
an Timing Driven routing. I also used the "Optimize by timing" options
in the menu "place Cells"
2 I exported pdef, setload, verilog and sdf file to DC
3 In DC i read all this informations and I performed a reoptimize
-in_place command!
4 What do I have to do next?????

Please can someone help me?

You write out another verilog gate level netlist and read it into SE
with "verilog eco". Then do an eco place in case some cells got bigger
or buffers were inserted and than another wroute.

 

[paololoceri@yahoo.it]

Do I have to restart from the routed design or just from the placed
one?
And what about import->verilogECO and place->ECO options? I know of
course that it will depend on the situation, but can anyone give me a
tip about a default setting?

thanks a lot
Paolo


mk wrote:

On 9 Mar 2005 08:23:19 -0800, "paololoceri@yahoo.it"
paololoceri@yahoo.it> wrote:

Hi all!
I am on the run to make a post layout optimization for one of my
designs!
I need some infos about incremental place and route using data
coming
from DC.
At the moment:
1 I performed Global place&route using Timing Driven placement
option
an Timing Driven routing. I also used the "Optimize by timing"
options
in the menu "place Cells"
2 I exported pdef, setload, verilog and sdf file to DC
3 In DC i read all this informations and I performed a reoptimize
-in_place command!
4 What do I have to do next?????

Please can someone help me?

You write out another verilog gate level netlist and read it into SE
with "verilog eco". Then do an eco place in case some cells got
bigger
or buffers were inserted and than another wroute.