signed multiplier with older Verilog versions

[Aki Hyyryläinen]

Hi,

Verilog2001 has a signed datatype like VHDL, and signed arithmetic
multiplications are trivial, e.g.

result <= signed(a_in) * signed(b_in);

But is there a way (without external sign handling logic) in older Verilog
versions to perform a signed multiplication? Using designware components
like DW_02 is not an option...

Thanks!

-Aki

 

[Aki Hyyryläinen]

and if you are trying to synthesize your design, you should make sure
that
your synthesis tool uses a proper circuit for the multiplier.

I am, and this, in fact, is essentially the core of the problem. How to
write such code without signed type or component mapping that generates a
signed multiplier?

-Aki


Aki Hyyryläinen wrote:

Hi,

Verilog2001 has a signed datatype like VHDL, and signed arithmetic
multiplications are trivial, e.g.

result <= signed(a_in) * signed(b_in);

But is there a way (without external sign handling logic) in older Verilog
versions to perform a signed multiplication? Using designware components
like DW_02 is not an option...

Thanks!

-Aki

 

[Libby]

On Sun, 03 Jul 2005 23:11:46 +0300, Aki Hyyryläinen wrote:

But is there a way (without external sign handling logic) in older Verilog
versions to perform a signed multiplication? Using designware components
like DW_02 is not an option...

One technique is to take the absolute value of the two operands, perform

an unsigned multiply, and fix the answer by negating the product if the
operands had different signs.

 

[HDLGuru]

Hi,

if you are just trying to simulate your code, you can use the following
trick:

suppose you are trying to multiply two n-bit numbers where both are in
2's complement format. Sign extend both numbers to 2n bits. multiply
them (unsigned) and choose the lower 2n bits of the result as the
result of signed multiplication.

and if you are trying to synthesize your design, you should make sure
that
your synthesis tool uses a proper circuit for the multiplier.

regards

--Nima


Aki Hyyryläinen wrote:

Hi,

Verilog2001 has a signed datatype like VHDL, and signed arithmetic
multiplications are trivial, e.g.

result <= signed(a_in) * signed(b_in);

But is there a way (without external sign handling logic) in older Verilog
versions to perform a signed multiplication? Using designware components
like DW_02 is not an option...

Thanks!

-Aki

 

[HDLGuru]

You can still use the trick above to create a signed multiplier, but it
will have the hardware complexity of a 2n- by 2n-bit multiplier. you
can write it this way

module sm(o, a, b);

// declarations
parameter len = 8;

input [len-1:0] a, b;
output [2*len-1:0] o;


// datapath
wire [2*len-1:0] se_a = { {len{a[len-1]}}, a }; // sign extension of a
wire [2*len-1:0] se_b = { {len{b[len-1]}}, b }; // sign extension of b
assign o = se_a * se_b;

endmodule


But, every synthesis tool has its own unique directives to do signed
arithmetics. for example LeonardoSpectrum has a `signed directive that
will make sure that signed version of an arithmetic circuit is used in
the design. For example

assign o = a * `signed b;

will perform a signed multiplication.