Signed Multiplication in a Virtex-II Multiplier.

[Anil Khanna]

I am trying to construct a 6x6 signed multiplier using the Virtex II block
multipliers. I know that the V-II multipliers are inherently a 2's
complement signed multiplier. However, my question is - by how much should I
sign-extend the inputs?

Example:
Input A - 6 bit
Input B - 6 bit
Output B- 12 bit

Should I connect the remaining ports of the multiplier input (A(7:18)) to
A(6) or just A(7:12) to A(6)? The handbook suggests that the sign-extension
of the inputs is done till the width of the output. Is this enough or should
I do it till the physical width of the multiplier?

Thanks

Anil

 

[Peng Cong]

If you use Xilinx IP Core
A - 6 bit B - 6 bit B- 12 bit
is enough


"Anil Khanna" <anil_khanna@mentor.com> Đ´ČëĎűϢĐÂÎĹ
:3f906a1c$1@solnews.wv.mentorg.com...

I am trying to construct a 6x6 signed multiplier using the Virtex II block
multipliers. I know that the V-II multipliers are inherently a 2's
complement signed multiplier. However, my question is - by how much should
I
sign-extend the inputs?

Example:
Input A - 6 bit
Input B - 6 bit
Output B- 12 bit

Should I connect the remaining ports of the multiplier input (A(7:18)) to
A(6) or just A(7:12) to A(6)? The handbook suggests that the
sign-extension
of the inputs is done till the width of the output. Is this enough or
should
I do it till the physical width of the multiplier?

Thanks

Anil

 

[Peng Cong]

If you use Xilinx IP Core
A - 6 bit B - 6 bit B- 12 bit
is enough

"Anil Khanna" <anil_khanna@mentor.com> Đ´ČëĎűϢĐÂÎĹ
:3f906a1c$1@solnews.wv.mentorg.com...

I am trying to construct a 6x6 signed multiplier using the Virtex II block
multipliers. I know that the V-II multipliers are inherently a 2's
complement signed multiplier. However, my question is - by how much should
I
sign-extend the inputs?

Example:
Input A - 6 bit
Input B - 6 bit
Output B- 12 bit

Should I connect the remaining ports of the multiplier input (A(7:18)) to
A(6) or just A(7:12) to A(6)? The handbook suggests that the
sign-extension
of the inputs is done till the width of the output. Is this enough or
should
I do it till the physical width of the multiplier?

Thanks

Anil

 

[Anil Khanna]

Thanks for the reply.

However, I am not using the Xilinx Coregen!
Anyways, I figured out the answer to this question and now I have another Q.

The handbook claims that there are certain submodules (of the MULT18X18S)
available for use. These are submodules like MULT4X4 etc. How does one get
access to this and what is the primitive name?

Anil


"Peng Cong" <pc_dragon@sohu.com> wrote in message
news:bmqfru$j8h$1@news.yaako.com...

If you use Xilinx IP Core
A - 6 bit B - 6 bit B- 12 bit
is enough

"Anil Khanna" <anil_khanna@mentor.com> Đ´ČëĎűϢĐÂÎĹ
:3f906a1c$1@solnews.wv.mentorg.com...
I am trying to construct a 6x6 signed multiplier using the Virtex II
block
multipliers. I know that the V-II multipliers are inherently a 2's
complement signed multiplier. However, my question is - by how much
should
I
sign-extend the inputs?

Example:
Input A - 6 bit
Input B - 6 bit
Output B- 12 bit

Should I connect the remaining ports of the multiplier input (A(7:18))
to
A(6) or just A(7:12) to A(6)? The handbook suggests that the
sign-extension
of the inputs is done till the width of the output. Is this enough or
should
I do it till the physical width of the multiplier?

Thanks

Anil

 

[Peng Cong]

Are you sure? I look into the datasheet of Multiplier Generator V6.0,
did not see anything about submodules

"Anil Khanna" <anil_khanna@mentor.com> Đ´ČëĎűϢĐÂÎĹ
:3f923e9f$1@solnews.wv.mentorg.com...

Thanks for the reply.

However, I am not using the Xilinx Coregen!
Anyways, I figured out the answer to this question and now I have another
Q.

The handbook claims that there are certain submodules (of the MULT18X18S)
available for use. These are submodules like MULT4X4 etc. How does one get
access to this and what is the primitive name?

Anil


"Peng Cong" <pc_dragon@sohu.com> wrote in message
news:bmqfru$j8h$1@news.yaako.com...
If you use Xilinx IP Core
A - 6 bit B - 6 bit B- 12 bit
is enough

"Anil Khanna" <anil_khanna@mentor.com> Đ´ČëĎűϢĐÂÎĹ
:3f906a1c$1@solnews.wv.mentorg.com...
I am trying to construct a 6x6 signed multiplier using the Virtex II
block
multipliers. I know that the V-II multipliers are inherently a 2's
complement signed multiplier. However, my question is - by how much
should
I
sign-extend the inputs?

Example:
Input A - 6 bit
Input B - 6 bit
Output B- 12 bit

Should I connect the remaining ports of the multiplier input (A(7:18))
to
A(6) or just A(7:12) to A(6)? The handbook suggests that the
sign-extension
of the inputs is done till the width of the output. Is this enough or
should
I do it till the physical width of the multiplier?

Thanks

Anil

 

[Anil Khanna]

Look in the handbook. This has more infocompared to the datasheet.
"Peng Cong" <pc_dragon@sohu.com> wrote in message
news:bmvf0o$1o5b$1@mail.cn99.com...

Are you sure? I look into the datasheet of Multiplier Generator V6.0,
did not see anything about submodules

"Anil Khanna" <anil_khanna@mentor.com> Đ´ČëĎűϢĐÂÎĹ
:3f923e9f$1@solnews.wv.mentorg.com...
Thanks for the reply.

However, I am not using the Xilinx Coregen!
Anyways, I figured out the answer to this question and now I have
another
Q.

The handbook claims that there are certain submodules (of the
MULT18X18S)
available for use. These are submodules like MULT4X4 etc. How does one
get
access to this and what is the primitive name?

Anil


"Peng Cong" <pc_dragon@sohu.com> wrote in message
news:bmqfru$j8h$1@news.yaako.com...
If you use Xilinx IP Core
A - 6 bit B - 6 bit B- 12 bit
is enough

"Anil Khanna" <anil_khanna@mentor.com> Đ´ČëĎűϢĐÂÎĹ
:3f906a1c$1@solnews.wv.mentorg.com...
I am trying to construct a 6x6 signed multiplier using the Virtex II
block
multipliers. I know that the V-II multipliers are inherently a 2's
complement signed multiplier. However, my question is - by how much
should
I
sign-extend the inputs?

Example:
Input A - 6 bit
Input B - 6 bit
Output B- 12 bit

Should I connect the remaining ports of the multiplier input
(A(7:18))
to
A(6) or just A(7:12) to A(6)? The handbook suggests that the
sign-extension
of the inputs is done till the width of the output. Is this enough
or
should
I do it till the physical width of the multiplier?

Thanks

Anil