Signed Division VHDL/FPGA

[Dan Nilsen]

Hello.

Does anyone have a synthesizable implementation of 2's complement
integers for FPGA? The integers in question are of std_logic_vector of
different number of bits. It does not necessarily need any carry as
the precision I need isn't very crucial, but the sign is of course
important.

Would be good if anyone has any useful source, or if someone can point
me in the direction of an algorithm for this.

Cheers,

Dan

 

[Praveen]

I suggest you post this question on comp.arch.fpga or comp.dsp group.
You might get some replies..