A
ATran
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I have an unsigned 8-bit comparator in verilog, How would I change it
to become a signed 8-bit comparator?
to become a signed 8-bit comparator?
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well you can use the two sign bits and make 2 to 1 mux withI have an unsigned 8-bit comparator in verilog, How would I change it
to become a signed 8-bit comparator?
if eqn is (a>b)?
Shouldn't it be the positive one is greater if the signs are different?st0p@hotmail.com (ATran) wrote in message news:<425982b8.0411212030.29fb1a19@posting.google.com>...
I have an unsigned 8-bit comparator in verilog, How would I change it
to become a signed 8-bit comparator?
if eqn is (a>b)?
well you can use the two sign bits and make 2 to 1 mux with
if both are positive select the comparator output,
if both are negetive invert the comparator ouput,
if they are different and a is +ve then select comparator output.
if they are different and b is +ve then select not of comparator output.
Or I think you could save the inverters by feeding the sign bitAnyway, invert the sign bits and do an unsigned compare.
In FPGA designs, inverters are free in just about every case,glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<co2j30$is3$1@gnus01.u.washington.edu>...
Anyway, invert the sign bits and do an unsigned compare.
Or I think you could save the inverters by feeding the sign bit
of operand a in as the MSB of operand b, and vice versa.