Signals not seen as used during synthesis

L

laserbeak43

Guest
Hello,
I have some source code that has some inputs and registers that
are made in seperate module files and tied together, and even thought
it synthesises, i get warnings about signals not being used and they
will be tied to ground or similar. here's an example:
//------------------------------------------------------------------------------------------------------------------------------------------
"Warning:Xst:647 - Input <rst> is never used. This port will be
preserved and left unconnected if it belongs to a top-level block or
it belongs to a sub-block and the hierarchy of this sub-block is
preserved."
//-----------------------------------------------------------------------------------------------------------------------------------------
This code that the input port is used with.
module LCDInit(input rst, input clki ... );
......
;;;;
always @(negedge rst)
begin
cnt <= 0;
init <= 1;
state <= 0;
end
endmodule

Another fromt he same
Module----------------------------------------------------------------------------------------------
WARNING:Xst:647 - Input <clki> is never used. This port will be
preserved and left unconnected if it belongs to a top-level block or
it belongs to a sub-block and the hierarchy of this sub-block is
preserved.
//-----------------------------------------------------------------------------------------------------------------------------------------

always @(posedge clki)
begin
if(init)
begin
.......
//---------------------------------------------------------------------------------------------------------------------------------
and all of these modules have instances in a top-level module and the
ins and outs are directly stimulated(if i've set up the module
instances correctly):
//----------------------------------------------------------------------------------------------------------------------------------
module LCD(input reset, //start power on initialization
input clk, //default 50MHz clock
.........
......
LCDInit init(.clki(clk), .rst(reset), ...);
//--------------------------------------------------------------------------------------------------------------------------------------
So this has me thinking that i might have some bugs in my copy of ISE?
I'm using 11.1 and can't seem to update using the updater or manual
download cause it always crashes, so i don't know if this is the
problem. I've also uploaded the code
:
http://laserbeak43.webs.com/Verilog/LCD.zip
if you could help, I'd really appreciate it.
Thanks,
Malik
 
On Oct 18, 10:52 pm, laserbeak43 <laserbea...@gmail.com> wrote:
Hello,
    I have some source code that has some inputs and registers that
are made in seperate module files and tied together, and even thought
it synthesises, i get warnings about signals not being used and they
will be tied to ground or similar. here's an example:
//------------------------------------------------------------------------------------------------------------------------------------------
"Warning:Xst:647 - Input <rst> is never used. This port will be
preserved and left unconnected if it belongs to a top-level block or
it belongs to a sub-block and the hierarchy of this sub-block is
preserved."
//-----------------------------------------------------------------------------------------------------------------------------------------
This code that the input port is used with.
module LCDInit(input rst, input clki ... );
.....
;;;;
always @(negedge rst)
        begin
                cnt <= 0;
                init <= 1;
                state <= 0;
        end
endmodule

Another fromt he same
Module----------------------------------------------------------------------------------------------
WARNING:Xst:647 - Input <clki> is never used. This port will be
preserved and left unconnected if it belongs to a top-level block or
it belongs to a sub-block and the hierarchy of this sub-block is
preserved.
//-----------------------------------------------------------------------------------------------------------------------------------------

always @(posedge clki)
        begin
                if(init)
                begin
......
//---------------------------------------------------------------------------------------------------------------------------------
and all of these modules have instances in a top-level module and the
ins and outs are directly stimulated(if i've set up the module
instances correctly):
//----------------------------------------------------------------------------------------------------------------------------------
module LCD(input reset,         //start power on initialization
                                input clk,                              //default 50MHz clock
........
.....
LCDInit init(.clki(clk), .rst(reset), ...);
//--------------------------------------------------------------------------------------------------------------------------------------
So this has me thinking that i might have some bugs in my copy of ISE?
I'm using 11.1 and can't seem to update using the updater or manual
download cause it always crashes, so i don't know if this is the
problem. I've also uploaded the code
:http://laserbeak43.webs.com/Verilog/LCD.zip
if you could help, I'd really appreciate it.
Thanks,
Malik
Click to expand...
I'm surprised you don't actually get errors synthesizing this code.
Usually XST will complain about driving the same signal from more
than one always block. If you want to make flip-flops with async
reset, you should follow the standard template:

always @ (posedge clk or posedge rst)
if (rst)
begin
Q <= reset_state;
end
else
begin
Q <= D_input;
end

Example has active high reset, but you can use negedge rst and
if (!rst) for active low reset. If XST has thrown out one of
your always blocks it could explain the warnings.

regards,
Gabor
 
Thanks a lot for looking,
I never did thank you for your help. I'm one step closer to
understanding what I did wrong.
I still have warnings, but I'll start another topic for those.

On Oct 19, 10:14 am, gabor <ga...@alacron.com> wrote:
On Oct 18, 10:52 pm, laserbeak43 <laserbea...@gmail.com> wrote:





Hello,
    I have some source code that has some inputs and registers that
are made in seperate module files and tied together, and even thought
it synthesises, i get warnings about signals not being used and they
will be tied to ground or similar. here's an example:
//-------------------------------------------------------------------------­-----------------------------------------------------------------
"Warning:Xst:647 - Input <rst> is never used. This port will be
preserved and left unconnected if it belongs to a top-level block or
it belongs to a sub-block and the hierarchy of this sub-block is
preserved."
//-------------------------------------------------------------------------­----------------------------------------------------------------
This code that the input port is used with.
module LCDInit(input rst, input clki ... );
.....
;;;;
always @(negedge rst)
        begin
                cnt <= 0;
                init <= 1;
                state <= 0;
        end
endmodule

Another fromt he same
Module---------------------------------------------------------------------­-------------------------
WARNING:Xst:647 - Input <clki> is never used. This port will be
preserved and left unconnected if it belongs to a top-level block or
it belongs to a sub-block and the hierarchy of this sub-block is
preserved.
//-------------------------------------------------------------------------­----------------------------------------------------------------

always @(posedge clki)
        begin
                if(init)
                begin
......
//-------------------------------------------------------------------------­--------------------------------------------------------
and all of these modules have instances in a top-level module and the
ins and outs are directly stimulated(if i've set up the module
instances correctly):
//-------------------------------------------------------------------------­---------------------------------------------------------
module LCD(input reset,         //start power on initialization
                                input clk,                              //default 50MHz clock
........
.....
LCDInit init(.clki(clk), .rst(reset), ...);
//-------------------------------------------------------------------------­-------------------------------------------------------------
So this has me thinking that i might have some bugs in my copy of ISE?
I'm using 11.1 and can't seem to update using the updater or manual
download cause it always crashes, so i don't know if this is the
problem. I've also uploaded the code
:http://laserbeak43.webs.com/Verilog/LCD.zip
if you could help, I'd really appreciate it.
Thanks,
Malik

I'm surprised you don't actually get errors synthesizing this code.
Usually XST will complain about driving the same signal from more
than one always block.  If you want to make flip-flops with async
reset, you should follow the standard template:

always @ (posedge clk or posedge rst)
if (rst)
  begin
    Q <= reset_state;
  end
else
  begin
    Q <= D_input;
  end

Example has active high reset, but you can use negedge rst and
if (!rst) for active low reset.  If XST has thrown out one of
your always blocks it could explain the warnings.

regards,
Gabor
Click to expand...
 
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