signals and variables

[David Binnie]

Hi all,

I'm looking at the difference between signals and variables.
I had always presumed synthesis must turn all variables into signals.

When I run this bit of code:


architecture behv of sig_var is

signal sig_s1: std_logic;
begin
proc1: process(d1,d2,d3)
variable var_s1: std_logic;
begin
var_s1 := d1 and d2;
res1 <= var_s1 xor d3;
end process;

proc2: process(d1,d2,d3)
begin
sig_s1 <= d1 and d2;
res2 <= sig_s1 xor d3;
end process;

end behv;

The output res2 is delayed cf the output res1 as theory would predict.
I didn't think this would synthesise but the Xilinx RTL Viewer
produced the same gate level description for rs1 and res2 but added a box
called Alias
at the output of res1.

What is this Alias box, presumably it does not exist in reality or have
Xilinx invented time travel ?

 

[Rolf Eike Beer]

Von David Binnie:

Hi all,

I'm looking at the difference between signals and variables.
I had always presumed synthesis must turn all variables into signals.

The difference will show up better if you use clocked processes. A
variable will get it's result immediately, a signal will be passed
through a register so you can't see the new value until the next cycle.

A variable will be just "wire" (and probably then a register if the value
is needed in next cycle again), a signal will pass through a synchronous
register or something. Think a,b being signals and a is set to '1' in
last cycle.

a <= '0';
b <= a;

will give you (a,b) = "01" in next clock cycle. If a would be a variable
the result will be "11".

Eike

 

[Mike Treseler]

David Binnie wrote:

I'm looking at the difference between signals and variables.
I had always presumed synthesis must turn all variables into signals.

No. Synthesis does whatever is necessary to
create a netlist that sims the same as your code.

When I run this bit of code:

Consider adding a clock input and
synchronizing your processes, or better
yet, do it all in one process.

-- Mike Treseler

 

[Ralf Hildebrandt]

David Binnie wrote:

I'm looking at the difference between signals and variables.

Variables get their values immediately, signals in the next delta delay.

architecture behv of sig_var is

signal sig_s1: std_logic;
begin
proc1: process(d1,d2,d3)
variable var_s1: std_logic;
begin
var_s1 := d1 and d2;
res1 <= var_s1 xor d3;
end process;

proc2: process(d1,d2,d3)
begin
sig_s1 <= d1 and d2;
res2 <= sig_s1 xor d3;
end process;

end behv;

The output res2 is delayed cf the output res1 as theory would predict.
I didn't think this would synthesise but the Xilinx RTL Viewer
produced the same gate level description for rs1 and res2 but added a box
called Alias
at the output of res1.

What you have is a difference between simulation and synthesis.
Simulations stays stick to the sensitivity list. Therefore for proc2
sig_s1 and res2 get new values after the process is triggered in the
next delta delay. For res2 the _old_ value of sig_s1 is evaluated
(because the new value is not yet assigned).
Synthesis does not care about sensitivity lists, but gives you a
warning, that sig_s1 is read without beeing in the sensitivity list or
proc2.
So, if you want to have same behavior of synthesis, use:

1) a complete synsitivity list

proc2: process(d1,d2,d3,sig_s1)
begin
sig_s1 <= d1 and d2;
res2 <= sig_s1 xor d3;
end process;

2) a variable instead of a signal

proc2: process(d1,d2,d3,sig_s1)
variable sig_temp : std_logic;
begin
sig_temp := d1 and d2;
res2 <= sig_temp xor d3;
end process;

Solution 1 lets you access sig_s1 outside the process, but the process
is triggered twice evertime: 1st, if d1,d2 or d3 changes and in the next
delta delay, when sig_s1 has changed. -> Increased simulation time
compared to solution 2.

Ralf