Signal Width

[Matthew Hicks]

Is there any easy way in Verilog to get the width of a wire, reg, or parameter
value? I am trying to create a parameter that holds the width of another
parameter, which is calculated at compile/synthesis time.


---Matthew Hicks

 

[Muzaffer Kal]

On Sat, 4 Oct 2008 13:55:57 +0000 (UTC), Matthew Hicks
<mdhicks2@uiuc.edu> wrote:

Is there any easy way in Verilog to get the width of a wire, reg, or parameter
value? I am trying to create a parameter that holds the width of another
parameter, which is calculated at compile/synthesis time.

You should be able to do it with PLI but that wouldn't be of any help
for synthesis. I think you should just compute the second parameter's
width at the same time as the first one using the same inputs. Verilog
doesn't support any notion of late binding or any similar feature so
all info necessary should be available to you without any indirection
necessary. If this is not very helpful, add some more details to your
question.

 

[Mike Treseler]

Matthew Hicks wrote:

Is there any easy way in Verilog to get the width of a wire, reg, or
parameter value? I am trying to create a parameter that holds the width
of another parameter, which is calculated at compile/synthesis time.

It's easy in vhdl, but not in verilog.
This might help some:
http://www.google.com/search?q=Verilog+2001+named+parameter

-- Mike Treseler

 

[nlzjk]

"Matthew Hicks" <mdhicks2@uiuc.edu> wrote in message
news:6004390c54e58caf41626d78a76@news.acm.uiuc.edu...

Is there any easy way in Verilog to get the width of a wire, reg, or
parameter value? I am trying to create a parameter that holds the width
of another parameter, which is calculated at compile/synthesis time.

Regrettably, VHDL can do this easily through queryable attributes ('width)
Verilog has no equivalent query-method.

Systemverilog adds several system-tasks which immitate the VHDL-attributes:
$bits()
$left()
$right()
$high()
$low()
$size(), $dimension [for arrays]

Of course, if your testbench environment doesn't permit Systemverilog, then
you're stuck.

 

[Mike Treseler]

nlzjk wrote:

Regrettably, VHDL can do this easily through queryable attributes ('width)

.... for simulation and synthesis.

Verilog has no equivalent query-method.

That is the regrettable part.
As is the depth of the Systemverilog synthesis subset.

-- Mike Treseler

 

[dm]

On Oct 4, 4:55 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote:

Is there any easy way in Verilog to get the width of a wire, reg, or parameter
value?  I am trying to create a parameter that holds the width of another
parameter, which is calculated at compile/synthesis time.

---Matthew Hicks

You could try $bits() -- some simulators support such essential
SystemVerilog extensions.

 

[Matthew Hicks]

Unfourtanetly, that doesn't work in my environment... "Non-standard system
call"


---Matthew Hicks

On Oct 4, 4:55 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote:

Is there any easy way in Verilog to get the width of a wire, reg, or
parameter value? I am trying to create a parameter that holds the
width of another parameter, which is calculated at compile/synthesis
time.

---Matthew Hicks

You could try $bits() -- some simulators support such essential
SystemVerilog extensions.

 

[Andy]

On Oct 5, 11:17 pm, "nlzjk" <nl...@anon.net> wrote:

Regrettably, VHDL can do this easily through queryable attributes ('width)
Verilog has no equivalent query-method.

It is most certainly not regrettable that VHDL can do this easily...

Andy