signal spy

[yong]

I have VHDL memory inside of Verilog environment.
I use signal spy to drive ($init_singal_driver) and watch
($init_signal_spy) some signal and it work find.
But I am trying to initialize memory using $init_signal_driver but I am
getting error.

Is it possible to using signal spy to write to memory?

initial begin
init_mem_value = 64'hfffffffffffffabcd;

$init_signal_driver("init_mem_value",
"/testtop/ram00/M1/i_memArray[0]", , , 1);

end

Thanks,

--Yong

 

[Ajeetha]

Looks like a limitation as of today. Try using:

1. TCL inside Modelsim, especially for memory load, there are special
commands
2. SVA Bind can work with VHDL and that can do this quite nicely. I
don't have an example, but can make one if needed. But will take me a
week or so as I'm quite busy with team building for my company right
now!

HTH
Ajeetha, CVC
www.noveldv.com

yong wrote:

I have VHDL memory inside of Verilog environment.
I use signal spy to drive ($init_singal_driver) and watch
($init_signal_spy) some signal and it work find.
But I am trying to initialize memory using $init_signal_driver but I am
getting error.

Is it possible to using signal spy to write to memory?

initial begin
init_mem_value = 64'hfffffffffffffabcd;

$init_signal_driver("init_mem_value",
"/testtop/ram00/M1/i_memArray[0]", , , 1);

end

Thanks,

--Yong