Signal issues

[aleksa]

I have a PCB with big pads all around the
FPGA (XC3S50A VQFP 100) so I can solder
the wires on the pads and do some testing.

I've done plenty of tests, possibly damaging the chip.
After the last soldering, the test prog didn't work anymore.

I've zipped some data bus signal photos here:
http://www24.zippyshare.com/v/80404483/file.html

1V / 100ns, 0V on 2nd hor. line.

VCCINT around 1.15V
VCCINT, VCCAUX around 3.2V


D7.jpg:
-------
Besides one input-only signal, D7 is the only I/O
located in Bank 0, P78. It differs from "others.jpg".
VCCINT and VCCIO looks the same as in all other banks.
Wire length is the same as the rest.


D4-D6.jpg:
----------
This photo is taken with drive strength of 4mA and more.
It only works if I use 2mA - and it looks like "others.jpg"
D4-P64, D5-P71, D6-P73.


others.jpg:
----------
This is how all the other signals look, which is about normal.


I've been using all the pins at 12mA at first,
for at least a week, even though WASSO said it
was overdrive. Could that cause damage to the pins?

 

[Gabor]

The IO pins are pretty rugged in terms
of output drive to a low impedance load.
The WASSO limit has to do with ground
bounce and should not affect the long
term chip reliability.

If I had to guess, it is more likely that
the damage was caused by ESD from an un-
grounded soldering iron.

-- Gabor

 

[aleksa]

"Gabor" <gabor@alacron.com> wrote in message news:0e538dee-d282-49ce-a340-7c4d851399a4@glegroupsg2000goo.googlegroups.com...

The IO pins are pretty rugged in terms
of output drive to a low impedance load.
The WASSO limit has to do with ground
bounce and should not affect the long
term chip reliability.

If I had to guess, it is more likely that
the damage was caused by ESD from an un-
grounded soldering iron.

-- Gabor

I have D4-D6 now working at all drive strengths,
meaning that the chip wasn't damaged...
Surely it hasn't fixed itself, right?

I had ringing on RD and WR clocks, and also induction in those lines.
After adding series resistors, all problems have vanished.

For example, I did a test: on risingedge(WR) reg <= reg +1.
The CPU was only reading the reg all the time
and the value kept increasing.

I think I understand now the behavior that D4-D6 were showing:
1. CPU did a READ.
2. FPGA updated DATAOUT and placed it on DBUS.
3. induction caused WRITE to activate (and change REG0).
4. ringing on RD caused another READ (with now changed data).

if rising_edge(CLKWR) then
if CS='0' then
if ADDR=0 then REG0 <= DBUS; end if;
end if;
end if;

if falling_edge(CLKRD) then
if CS='0' then
if ADDR=0 then DATAOUT <= REG0; end if;
end if;
end if;

DBUS <= DATAOUT when (CLKRD='0' and CS='0') else "ZZZZZZZZZZZZZZZZ";

Why is D7 different, I don't know...