Signal Generator using FPGA and DAC

S

Sheetal

Guest
hi..I'm a university student familiar with the only the basics of VHDL
and FPGA implementation..For my project, I'm trying a make a sine
wave, ramp, triangular and square wave generator which outputs
required wave of required amplitude and required frequency

The FPGA is connected with DAC thru I2C bus..

The development board (nanoboard) has on- board freq of 20 mhz...now the
dac being connected to the I2c bus can work upto max 400 Mhz..so a
suitable clock divisor has to be implemented ..thus a low frequency
can be used as SCL input to DAC..

a)Now, for the sine and square wave, I'm assuming that we can use the
same look-up table(values ranging from 0 to 256)for the output values
of DAC.for

obtaining different frequencies, only the SCL needs to be changed .
i.e.if SCl rate is high, the DAC would output from 0 to 256, then to 0
at a faster rate,

if SCL is low, it would output the same values, but with some delay.
THus, variable frequency can be obtained by changing SCL rate..am I
correct in assuming so?

b)If this is correct, can anyone please tell me the relationship
between SCL and output wave frequency..if such a formula/well defined
relationship does exist

c) Also, can anyone tell me about a good link for a simple tutorial on
implementing look-up table?I did find some on the web, but they all
seemed to be complicated..either because they ARE..or because my mind
has gone all-blank right now, with the submission date coming so
near..

Any help at this time would be hugely appreciated

Kind Regards,
Sheetal
 
On Apr 24, 6:23 am, Sheetal <sheetalgandhi...@gmail.com> wrote:
hi..I'm a university student familiar with the only the basics of VHDL
and FPGA implementation..For my project, I'm trying a make a sine
wave, ramp, triangular and square wave generator which outputs
required wave of required amplitude and required frequency

The FPGA is connected with DAC thru I2C bus..

The development board (nanoboard) has on- board freq of 20 mhz...now the
dac being connected to the I2c bus can work upto max 400 Mhz..so a
suitable clock divisor has to be implemented ..thus a low frequency
can be used as SCL input to DAC..

a)Now, for the sine and square wave, I'm assuming that we can use the
same look-up table(values ranging from 0 to 256)for the output values
of DAC.for

obtaining different frequencies, only the SCL needs to be changed .
i.e.if SCl rate is high, the DAC would output from 0 to 256, then to 0
at a faster rate,

if SCL is low, it would output the same values, but with some delay.
THus, variable frequency can be obtained by changing SCL rate..am I
correct in assuming so?

b)If this is correct, can anyone please tell me the relationship
between SCL and output wave frequency..if such a formula/well defined
relationship does exist

c) Also, can anyone tell me about a good link for a simple tutorial on
implementing look-up table?I did find some on the web, but they all
seemed to be complicated..either because they ARE..or because my mind
has gone all-blank right now, with the submission date coming so
near..

Any help at this time would be hugely appreciated

Kind Regards,
Sheetal
Click to expand...
I don't really understand how your system is setup... You have an I2C
bus between an FPGA and a 400M DAC? I2C typically runs around
400kHz. You will never be able to get samples to the DAC at at rate
of 400M samples using I2C

You need to read up on the I2C standard a bit perhaps. Typically
you'll transfer 1 byte per bus cycle. How many bits are the samples?

What FPGA are you using? I know Xilinx (and I suspect that's true for
Altera as well) has soft cores to generate sine waves in various
ways. You don't need to be bothered implementing your own look up
tables. Also you could use a cordic core (also a soft macro in
xilinx) to generate your sine waves (to avoid using memory).

Provide more details and I can try to help you

-Jakub
 
Hello Sheetal!!!

I m Hrishikesh . I along with two of my friends are also currently
trying to build a Function generator for my Final Year Engg course!!
The on- board crystal for our FPGA board is 6MHz. We are using Xilinx
FPGA Xc2s50 tq144 -6

I have been successful in generating
square wave upto 45kHz
sine wave with 128 sample pts for one cycle upto 12kHz
triangular wave with 128 sample points for one cycle upto 7.5kHz.

The main restrictions that we faced were
1. The on board clock is of too low frequency.
2. The floating point values are not synthesisable.For higher
frequency generation the count used for delays being floating point
values were approximated to integer values.This reduces the accuracy
of the frequencies generated.

We also have done duty cycle variation for sqare and triangular wave
though we have shown only 10,30,50 and 70% duty cycles. other values
can also be obtained

the DAC we have used is DAC0808.

Sorry but i really haven't tried out interfacing it to an I2C bus but
i'm sure u'll be succesful in doin that!!!
all the best!!!
 
Hrishi wrote:

I m Hrishikesh . I along with two of my friends are also currently
trying to build a Function generator for my Final Year Engg course!!
The on- board crystal for our FPGA board is 6MHz. We are using Xilinx
FPGA Xc2s50 tq144 -6

I have been successful in generating
square wave upto 45kHz
sine wave with 128 sample pts for one cycle upto 12kHz
triangular wave with 128 sample points for one cycle upto 7.5kHz.
Click to expand...
With a 6MHz clock and 150ns settling time, you should be able to
generate square waves in the low MHz range?!? And 128-sample/cycle waves
(of any shape) around 46kHz by my calculations.

The main restrictions that we faced were
1. The on board clock is of too low frequency.
Click to expand...
With a 150ns settling time you won't need a faster clock, and even if
you did you can use a DCM to multiply the clock internally.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
Sheetal wrote:

The development board (nanoboard) has on- board freq of 20 mhz...now
the dac being connected to the I2c bus can work upto max 400 Mhz..so
a suitable clock divisor has to be implemented ..thus a low frequency
can be used as SCL input to DAC..
Click to expand...
This is a Nanoboard-NB1?

You need to read up on the I2C bus. BTW the maximum clock rate on the
bus is 400kHz (not MHz) and taking a quick look at the data sheet, you
need to write a minimum of 3 bytes to the device to update a DAC output.
So the maximum rate you can output will be roughly 400k/(3*9) or 14kHz.

Opencores has an I2C controller that should get you up-and-running at
least. It interfaces to wishbone but generating simple wishbone cycles
is trivial.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
canadianJaouk wrote:

c) Also, can anyone tell me about a good link for a simple tutorial
on implementing look-up table?I did find some on the web, but they
all seemed to be complicated..either because they ARE..or because
my mind has gone all-blank right now, with the submission date
coming so near..
Click to expand...
Why do you need a lookup table?

For example, if you have a single 128-byte sine wave stored in an array,
you simply need to clock a counter to use as the array address (index)
at your sampling rate.

You could even clock this asynchronously to the process that writes the
DAC, so your DAC is updated at the same rate regardless of your sampling
rate. The usual precautions need to be taken when shuffling data across
clock domains of course...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
On May 2, 8:20 pm, Mark McDougall <m...@vl.com.au> wrote:

Why do you need a lookup table?

For example, if you have a single 128-byte sine wave stored in an array,
you simply need to clock a counter to use as the array address (index)
at your sampling rate.
Click to expand...
Your sine wave stored in an array is a lookup table!

By reversing the sign of the output, and the direction of the counter,
you can get by with only a quarter cycle of the wave due to symmetry.

Andy
 
Andy wrote:

Your sine wave stored in an array is a lookup table!
Click to expand...
Umm, not really. A lookup table generally implies an associated search
function for mapping one value to another - and an order of magnitude
more difficult to implement.

The sine wave in question is more akin to a waveform sample stored in,
for example, a ROM. Or you could do away with the addressing altogether
and use a circular shift-register.

By reversing the sign of the output, and the direction of the counter,
you can get by with only a quarter cycle of the wave due to symmetry.
Click to expand...
True.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
On May 3, 7:50 pm, Mark McDougall <m...@vl.com.au> wrote:
Andy wrote:
Your sine wave stored in an array is a lookup table!

Umm, not really. A lookup table generally implies an associated search
function for mapping one value to another - and an order of magnitude
more difficult to implement.

The sine wave in question is more akin to a waveform sample stored in,
for example, a ROM. Or you could do away with the addressing altogether
and use a circular shift-register.

By reversing the sign of the output, and the direction of the counter,
you can get by with only a quarter cycle of the wave due to symmetry.

True.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Click to expand...

Umm, yes; there are more complex look up tables than simple arrays,
but when an array is used to transform the input vector (address) into
the output vector (data element), it is in fact a look up table, and
if coded correctly will be implemented as a ROM or RAM in an FPGA.
Just because the search function is implemented very efficiently in
hardware (address decoding) does not mean there is no search function.

For all but the smallest tables, an addressed ROM/RAM (using
appropriate FPGA resources) is almost always more efficient than a
circular shift register.

Andy
 
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