"signal does not hold its value outside clock edge"

[Guilherme Corręa]

Hello.

I'm a begginer in VHDL and I'm with a problem in the compilation of my
description.
These are the errors:

Error: VHDL error at mult_seq_mf.vhd(62): can't infer register for
signal "entradaregB[7]" because signal does not hold its value outside
clock edge
Error: VHDL error at mult_seq_mf.vhd(62): can't infer register for
signal "entradaregB[6]" because signal does not hold its value outside
clock edge
Error: VHDL error at mult_seq_mf.vhd(62): can't infer register for
signal "entradaregB[5]" because signal does not hold its value outside
clock edge
Error: VHDL error at mult_seq_mf.vhd(62): can't infer register for
signal "entradaregB[4]" because signal does not hold its value outside
clock edge
Error: VHDL error at mult_seq_mf.vhd(62): can't infer register for
signal "entradaregB[3]" because signal does not hold its value outside
clock edge
Error: VHDL error at mult_seq_mf.vhd(62): can't infer register for
signal "entradaregB[2]" because signal does not hold its value outside
clock edge
Error: VHDL error at mult_seq_mf.vhd(62): can't infer register for
signal "entradaregB[1]" because signal does not hold its value outside
clock edge
Error: VHDL error at mult_seq_mf.vhd(62): can't infer register for
signal "entradaregB[0]" because signal does not hold its value outside
clock edge

All the errors are the same and the part of the description where the
error ocurrs is this:

entradaregB <= multB WHEN (clk'EVENT AND clk = '1' AND start = '1')
else soma(0) & multiplicador(n-1 DOWNTO 1);

If I take off the "clk'EVENT" it works, but I need to have a border
sensitive description.
Can anyone help me?
Thanks!

Guilherme Corręa.

 

[tln]

Hi Guilherme,

I'm assuming you got this error during synthesis. Because the end
result of your code is a hardware device, the code must be
synthesizable into hardware that exists on the FPGA/CPLD. The code you
have written does not describe a real synchronous element. To make a
register (not sure if this is what you want your code to do, but...):

reg_process: process (clk)
begin
if rising_edge(clk)
if start = '1' then
entradaregB <= multB;
else
entradaregB <= soma(0) & multiplicador(n-1 DOWNTO 1);
end if;
end if;
end process reg_process;

Registers can only change on a clock edge. Generally the only
asynchronous event that can change a register is a reset. You might
want to think about taking some training on FPGAs and VHDL. As a
beginner, if you don't have a good understanding of both the coding
methods to describe hardware and the hardware your code is configuring,
you will run into a lot of problems.

Good luck!

 

[Guilherme Corręa]

Ok, thank you.

The register is working now, but the result of all the description
isn't ok yet.
It's a description of a multiplier and the result of the multiplication
is wrong. I'll continue trying.

Thank you.

 

[Guilherme Corręa]

Ok, thank you.

The register is working now, but the result of all the description
isn't ok yet.
It's a description of a multiplier and the result of the multiplication
is wrong. I'll continue trying.

Thank you.

 

[Guilherme Corręa]

Ok, thank you.

The register is working now, but the result of all the description
isn't ok yet.
It's a description of a multiplier and the result of the multiplication
is wrong. I'll continue trying.

Thank you.

 

[Guilherme Corręa]

Ok, thank you.

The register is working now, but the result of all the description
isn't ok yet.
It's a description of a multiplier and the result of the multiplication
is wrong. I'll continue trying.

Thank you.