signal assigning question in FSM

[Elinore]

Hi

I have some confusing with mealy machine. I wrote some code (maybe with
some syntax error ) below.
I wish that after S2 cycle, address=1, offset=1, then transit into S3.
Also I hope that each statements work sequentially, (1)->(2)->(3).

------Description 1----------------------------------------------
architecture ...
type state is (S1, S2, S3)
signal S : state;
signal address: std_logic_vector(8 downto 0):= (others => '0');
signal offset: std_logic_vector(8 downto 0) := (others =>'0');
begin

process(...)
begin
...
case S is
when S1 => offset <= "00000001";
S<=S2;
when S2 => address <= address + offset; -- (1)
offset <= offset + '1'; -- (2)
if offset = '1' then S <= S3; enf if; -- (3)
when S3 ...
---------------------------------------------------------------

Above VHDL description is not working in simulation as I expect. When I
modify the code as following, it is working as I expect, ie, after S2
clock cycle, address is "1" and offset is "1".

------Description 2----------------------------------------------
...
when S2 => address <= address + offset; -- (1)
offset <= offset + '1'; -- (2)

when S3 => if offset = '1' then S <= S3; enf if; -- (4)
---------------------------------------------------------------

Question is that
it is unclear for me whether each of the statements (1),(2),(3)
'sequetially' or 'concurrently' works. Should I use variable in these
case (ie, there is dependency ) ?

Thanks