Signal Assertion with non blocking assignment

[apurv]

I hv defined two tasks in following manner.
I want to assert x for only one clock cycle.
However It's not working as it should
If i add one clock more the problem got solved. but is it right way of
doing it?

Thanks
apurv
-----------------------------------------------------------------

task temp;
begin
x <= 1'b1;
@(posedge host_intr_clk_i);
@(posedge host_intr_clk_i); // If i add this statement ,
logic works
temp1;
end
endtask

task temp1;
begin
x <= 1'b0;
end
endtask

 

[Neo]

one edge of clk_i will work provided you are enabling the task at
posedge of clk_i.

 

[apurv]

That is exactly what I am doing right now like

@(posedge clk_i);
temp;

Still It is not working

Neo wrote:

one edge of clk_i will work provided you are enabling the task at
posedge of clk_i.

 

[Neo]

You are calling the task after the clock edge and this
[code:1:bb3c008adc]
x <= 1'b1;
@(posedge clk_i);--(a)
[/code:1:bb3c008adc]
will make the value of x as '1' at the next clock edge(a), but also it
exits the task during that edge and you are making it '0' again next.
so the value '1' is over written with '0'.

 

[apurv]

why it is not making value of x as '1' at the end of simulation time
stamp but before next clock edge(a) comes
shouldn't it first make the value '1' and then wait for 1 clock

Neo wrote:

You are calling the task after the clock edge and this
[code:1:77ec5bf661]
x <= 1'b1;
@(posedge clk_i);--(a)
[/code:1:77ec5bf661]
will make the value of x as '1' at the next clock edge(a), but also it
exits the task during that edge and you are making it '0' again next.
so the value '1' is over written with '0'.

 

[Neo]

that is how NBAs work. use blocking assignments if thats what you want.

 

No, it will make the value x be 1 at the end of the time slice where it
is assigned. Why would you think it would wait for the next clock
edge? To get that, you would have to write it as

x <= @(posedge clk_i) 1'b1;

That is not what the example code says.

The described behavior does not appear to be correct, but we may not
have been given enough details about the code and the behavior to be
sure. Providing a very simple but complete testcase, including
something like a $monitor that displays all the value changes and
times, and the resulting output, would allow us to explain what is
happening.

 

[npk]

Your code works. I tried a testbench with a clk and the following --

task temp;
begin
x <= 1'b1;
@(posedge clk);
temp1;
end
endtask

task temp1;
begin
x <= 1'b0;
end
endtask


initial begin
x<= 0;
repeat (30) @(posedge clk);
temp;
repeat (30) @(posedge clk);
$finish;
end

The waveform shows x being asserted for one clock.

-Pradeep