A
apurv
Guest
I hv defined two tasks in following manner.
I want to assert x for only one clock cycle.
However It's not working as it should
If i add one clock more the problem got solved. but is it right way of
doing it?
Thanks
apurv
-----------------------------------------------------------------
task temp;
begin
x <= 1'b1;
@(posedge clk_i);
@(posedge clk_i); // If i add this statement , logic works
temp1;
end
endtask
task temp1;
begin
x <= 1'b0;
end
endtask
I want to assert x for only one clock cycle.
However It's not working as it should
If i add one clock more the problem got solved. but is it right way of
doing it?
Thanks
apurv
-----------------------------------------------------------------
task temp;
begin
x <= 1'b1;
@(posedge clk_i);
@(posedge clk_i); // If i add this statement , logic works
temp1;
end
endtask
task temp1;
begin
x <= 1'b0;
end
endtask