Sign extension

K

kclo4

Guest
Hi everybody,

I'd like to know if there is any smart way to extend the sign of
std_logic_vector

for exemple :

data_in : in std_logic_vector(11 downto 0);
data_out : out std_logic_vector(13 downto 0);

I want to adjust data_in to data_out size, so what i used to do is:

data_out <= data_in(11) & data_in(11) & data_in;

But for huge different size it's painfull and not really nice.
Is there a smarter way to do it?? May be I should do a function with a
loop that do it??

Thank you
 
kclo4 a écrit :
Hi everybody,

I'd like to know if there is any smart way to extend the sign of
std_logic_vector

for exemple :

data_in : in std_logic_vector(11 downto 0);
data_out : out std_logic_vector(13 downto 0);

I want to adjust data_in to data_out size, so what i used to do is:

data_out <= data_in(11) & data_in(11) & data_in;

But for huge different size it's painfull and not really nice.
Is there a smarter way to do it?? May be I should do a function with a
loop that do it??
Click to expand...
Use ieee.numeric_std package, signed vectors instead of std_logic_vector
and resize function.

data_out <= resize(data_in, data_out'length);

Nicolas
 
kclo4 a écrit :
Hi everybody,

I'd like to know if there is any smart way to extend the sign of
std_logic_vector

for exemple :

data_in : in std_logic_vector(11 downto 0);
data_out : out std_logic_vector(13 downto 0);

I want to adjust data_in to data_out size, so what i used to do is:

data_out <= data_in(11) & data_in(11) & data_in;

But for huge different size it's painfull and not really nice.
Is there a smarter way to do it?? May be I should do a function with a
loop that do it??

Thank you
Click to expand...
You have it for free in the std_logic_arith package:
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
[...]
data_out <= SXT(data_in, data_out'LENGTH);

You also have the EXT function, which is the simple extension function
_without_ sign extension.
 
Many users don't recommend using non-ieee packages such as
std_logic_arith, etc. that were developed by synopsys and compiled into
the ieee library without ieee permission/standardization. Since they
are not standard, their implementation can and does vary between
vendors of simulation and synthesis tools.

Better to type a little more and use ieee standard packages that are
uniform in their implementation across all vendors. If you need to keep
data_in and data_out as SLV:

data_out <= std_logic_vector(resize(signed(data_in), data_out'length));

Andy


OL wrote:
kclo4 a écrit :
Hi everybody,

I'd like to know if there is any smart way to extend the sign of
std_logic_vector

for exemple :

data_in : in std_logic_vector(11 downto 0);
data_out : out std_logic_vector(13 downto 0);

I want to adjust data_in to data_out size, so what i used to do is:

data_out <= data_in(11) & data_in(11) & data_in;

But for huge different size it's painfull and not really nice.
Is there a smarter way to do it?? May be I should do a function with a
loop that do it??

Thank you

You have it for free in the std_logic_arith package:
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
[...]
data_out <= SXT(data_in, data_out'LENGTH);

You also have the EXT function, which is the simple extension function
_without_ sign extension.
Click to expand...
 
Or if you use appropriately constrained subtypes of integer for
data_out and data_in:

data_out <= data_in;

Andy


Nicolas Matringe wrote:
kclo4 a écrit :
Hi everybody,

I'd like to know if there is any smart way to extend the sign of
std_logic_vector

for exemple :

data_in : in std_logic_vector(11 downto 0);
data_out : out std_logic_vector(13 downto 0);

I want to adjust data_in to data_out size, so what i used to do is:

data_out <= data_in(11) & data_in(11) & data_in;

But for huge different size it's painfull and not really nice.
Is there a smarter way to do it?? May be I should do a function with a
loop that do it??

Use ieee.numeric_std package, signed vectors instead of std_logic_vector
and resize function.

data_out <= resize(data_in, data_out'length);

Nicolas
Click to expand...
 
Nicolas Matringe schrieb:


Use ieee.numeric_std package, signed vectors instead of std_logic_vector
and resize function.

data_out <= resize(data_in, data_out'length);
Click to expand...
Respectively with std_ulogic_vector and the desired conversions:

-- either
data_out<=std_ulogic_vector(resize(unsigned(data_in), data_out'length));
-- or
data_out<=std_ulogic_vector(resize( signed(data_in), data_out'length));

(I only want to point it out that sign extension of std_ulogic_vectors
strongly depends on the fact whether signed or unsigned data
representation is desired.)

Ralf
 
There is no "sign extension" of unsigned representations, since there
is no sign bit. A resize of an unsigned representation to a larger size
just appends enough zeroes to fit, whereas sign extension replicates
the MSB enough times to fit.

The numeric_std.resize() function is overloaded to perform a sign
extend operation when called with a signed argument and return value
(assuming it is increasing the size of the argument).

Andy


Ralf Hildebrandt wrote:
Nicolas Matringe schrieb:


Use ieee.numeric_std package, signed vectors instead of std_logic_vector
and resize function.

data_out <= resize(data_in, data_out'length);

Respectively with std_ulogic_vector and the desired conversions:

-- either
data_out<=std_ulogic_vector(resize(unsigned(data_in), data_out'length));
-- or
data_out<=std_ulogic_vector(resize( signed(data_in), data_out'length));

(I only want to point it out that sign extension of std_ulogic_vectors
strongly depends on the fact whether signed or unsigned data
representation is desired.)

Ralf
Click to expand...
 
Andy schrieb:

There is no "sign extension" of unsigned representations, since there
is no sign bit. A resize of an unsigned representation to a larger size
just appends enough zeroes to fit, whereas sign extension replicates
the MSB enough times to fit.
Click to expand...
Yes, I know - but I wanted to point out, that nobody can say, what is
inside a std_logic_vector: just bits, signed or unsigned data.
And even adding zeros while resizing an unsigned vector is some kind of
sign extension, because an unsigned vector has always an implicit zero
as sign.

Ralf
 
kclo4 wrote:
Hi everybody,

I'd like to know if there is any smart way to extend the sign of
std_logic_vector

for exemple :

data_in : in std_logic_vector(11 downto 0);
data_out : out std_logic_vector(13 downto 0);

I want to adjust data_in to data_out size, so what i used to do is:

data_out <= data_in(11) & data_in(11) & data_in;

But for huge different size it's painfull and not really nice.
Is there a smarter way to do it?? May be I should do a function with a
loop that do it??

Thank you
Click to expand...

Don't need any libraries or loops if you do this:

data_out(11 downto 0) <= data_in;
data_out(13 downto 12) <= (13 downto 12 => data_in(11));
 
Ralf Hildebrandt a écrit :

(I only want to point it out that sign extension of std_ulogic_vectors
strongly depends on the fact whether signed or unsigned data
representation is desired.)
Click to expand...
I assumed that sign extension was only needed for signed vectors.

Nicolas
 
Thanks you all for your usefull answers,


Don't need any libraries or loops if you do this:

data_out(11 downto 0) <= data_in;
data_out(13 downto 12) <= (13 downto 12 => data_in(11));
Click to expand...
I like this way but shouldn't it be? :
data_out(13 downto 12) <= (others => data_in(11));

Probably both work?, I will try myself to check

Thanks

alexis
 
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