Sign extension in Modelsim

[valtih1978]

I was told that this will work in Verilog.

acc = { 3{ir[12]}, imm };

However, Modelsim reports an error: syntax error, unexpected ',',
expecting '}'

 

[valtih1978]

I know that $signed(imm) works. I just want to know what is wrong with
that method.

 

[Alan Fitch]

On 03/03/13 18:54, valtih1978 wrote:

I was told that this will work in Verilog.

acc = { 3{ir[12]}, imm };

However, Modelsim reports an error: syntax error, unexpected ',',
expecting '}'

Replication requires 2 pairs of braces, i.e.

acc = { {3{ir[12]}}, imm};

regards
Alan

--
Alan Fitch