Showing Verilog Enumerated Types

Hello,
Is it possible to define in Verilog that the sinulator (Modelsim) will
show the Enumerated Type and not value, i.e., in satates example, will
show st1, st2, sr3... instead of 0,1,2 ....
I know that the solution for this is to create virtual function in
Modelsim, but it's highly inconvenient.
I wonder if there is a trick to do it straight forward.

Thank you.

 

[NigelE]

On Nov 20, 2:24 pm, japon...@gmail.com wrote:

Hello,
Is it possible to define in Verilog that the sinulator (Modelsim) will
show the Enumerated Type and not value, i.e., in satates example, will
show st1, st2, sr3... instead of 0,1,2 ....
I know that the solution for this is to create virtual function in
Modelsim, but it's highly inconvenient.
I wonder if there is a trick to do it straight forward.

Thank you.

In 6.3 the capability was added to allow you to define your own radix.
Once defined, this radix is available alongside the predefined ones
and can be applied to any appropriate signal group

Have a look at 'radix define' in the Ref Manual

cheers

- Nigel

 

On 20 נובמבר, 17:20, NigelE <nigel_ell...@mentor.com> wrote:

On Nov 20, 2:24 pm, japon...@gmail.com wrote:

Hello,
Is it possible to define in Verilog that the sinulator (Modelsim) will
show the Enumerated Type and not value, i.e., in satates example, will
show st1, st2, sr3... instead of 0,1,2 ....
I know that the solution for this is to create virtual function in
Modelsim, but it's highly inconvenient.
I wonder if there is a trick to do it straight forward.

Thank you.

In 6.3 the capability was added to allow you to define your own radix.
Once defined, this radix is available alongside the predefined ones
and can be applied to any appropriate signal group

Have a look at 'radix define' in the Ref Manual

cheers

- Nigel

Hello Nigel,
Thank you for your tip.
But, as per my understanding, this is no different than virtual
function, meaning, it will be required to define radix for every state
machine in every different design.
Again, inconvenient.

Any other ideas?
Thanks

 

[NigelE]

On Nov 20, 3:43 pm, japon...@gmail.com wrote:

On 20 נובמבר, 17:20, NigelE <nigel_ell...@mentor.com> wrote:





On Nov 20, 2:24 pm, japon...@gmail.com wrote:

Hello,
Is it possible to define in Verilog that the sinulator (Modelsim) will
show the Enumerated Type and not value, i.e., in satates example, will
show st1, st2, sr3... instead of 0,1,2 ....
I know that the solution for this is to create virtual function in
Modelsim, but it's highly inconvenient.
I wonder if there is a trick to do it straight forward.

Thank you.

In 6.3 the capability was added to allow you to define your own radix.
Once defined, this radix is available alongside the predefined ones
and can be applied to any appropriate signal group

Have a look at 'radix define' in the Ref Manual

cheers

- Nigel

Hello Nigel,
Thank you for your tip.
But, as per my understanding, this is no different than virtual
function, meaning, it will be required to define radix for every state
machine in every different design.
Again, inconvenient.

Any other ideas?
Thanks- Hide quoted text -

- Show quoted text -

You define the enumeration once and then can apply it to any number of
buses or groups of signals.
I'm not sure how you can get away from from defining the enumeration
at least once ?

An alternative is to use SystemVerilog enumerated types, which gives
you the same GUI appearance but is embedded in your code.

cheers

- Nigel

 

[Andreas Ehliar]

On 2007-11-20, japonetz@gmail.com <japonetz@gmail.com> wrote:

Hello,
Is it possible to define in Verilog that the sinulator (Modelsim) will
show the Enumerated Type and not value, i.e., in satates example, will
show st1, st2, sr3... instead of 0,1,2 ....
I know that the solution for this is to create virtual function in
Modelsim, but it's highly inconvenient.
I wonder if there is a trick to do it straight forward.

Hi, defining your own virtual functions is quite annoying. However, I have
a small TCL script that can help you on my homepage:
http://www.da.isy.liu.se/~ehliar/stuff/

Look for stateenumerate.tcl and you will find the script and some images
of how it works. I have tested it in ModelSim 6.2g but I don't know if it
works in later versions of Modelsim. If it doesn't, let me know and I can
take a look at it to see if it is easy to fix.

/Andreas

 

On Nov 21, 7:03 am, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote:

On 2007-11-20, japon...@gmail.com <japon...@gmail.com> wrote:

Hello,
Is it possible to define in Verilog that the sinulator (Modelsim) will
show the Enumerated Type and not value, i.e., in satates example, will
show st1, st2, sr3... instead of 0,1,2 ....
I know that the solution for this is to create virtual function in
Modelsim, but it's highly inconvenient.
I wonder if there is a trick to do it straight forward.

Hi, defining your own virtual functions is quite annoying. However, I have
a small TCL script that can help you on my homepage:http://www.da.isy.liu.se/~ehliar/stuff/

Look for stateenumerate.tcl and you will find the script and some images
of how it works. I have tested it in ModelSim 6.2g but I don't know if it
works in later versions of Modelsim. If it doesn't, let me know and I can
take a look at it to see if it is easy to fix.

/Andreas

Hello Andreas,
Thank you, it helped.

Regards,
j