Showing value of loop iteration in assert statement

[dwerdna]

Hello all

I have this loop, but I cant work out to display the appropriate
channel to the screen when it fails..

The below example prints out the sentence as you see if (of course),
but I want the value of J. I've tried a few things, similar to when
you write values to a file, but havent been able to work it out

Thanks

Andrew

for J in 0 to 3 loop
if (exp_analog_channel(J) /= tb_channel_out(J)) then
assert false
report "Channel J failed " severity note; -- how do I get 'J' to
show value??
end if;
end loop;

 

All strings can be displayed in the report message

report "Channel"&conv_string(J)&"failed"
severity note;

 

[dwerdna]

Thanks! I'll give it a go

Andrew

 

[Ajeetha]

Just to add to it: Just in case your data type is different from a
scalar type, then 'image is not defined in VHDL-93. Ben has developed a
IMAGE pkg that can handle most of the cases, take a look at
http://www.vhdlcohen.com --> Models

HTH
Aji
http://www.noveldv.com