show-ahead FIFOs

B

Bertrik Sikken

Guest
Hi all,

I worked on a project using an Altera FPGA and I noticed that
their FIFOs have a 'show-ahead' feature. Currently I'm working
with an FPGA from Xilinx and I could not find a similar feature
on their FIFO's.

It seems to me such a feature can be very useful since it
allows you to get at the data one clock earlier.

Why don't the Xilinx FIFOs have such a feature?
(Or am I perhaps overlooking something some crucial
drawback of show-ahead FIFOs?)

Regards,
Bertrik Sikken
 
Bertrik Sikken wrote:
Hi all,

I worked on a project using an Altera FPGA and I noticed that
their FIFOs have a 'show-ahead' feature. Currently I'm working
with an FPGA from Xilinx and I could not find a similar feature
on their FIFO's.

It seems to me such a feature can be very useful since it
allows you to get at the data one clock earlier.

Why don't the Xilinx FIFOs have such a feature?
(Or am I perhaps overlooking something some crucial
drawback of show-ahead FIFOs?)
Click to expand...
A time machine ?

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
 
I think a better way to look a this is a FWFT (first word fall through)
- standard fifo trick - you can do these in any FPGA - transparent
latch, data available tpd after clock edge. No one can get data before
it exists.

Andrew

Bertrik Sikken wrote:

Hi all,

I worked on a project using an Altera FPGA and I noticed that
their FIFOs have a 'show-ahead' feature. Currently I'm working
with an FPGA from Xilinx and I could not find a similar feature
on their FIFO's.

It seems to me such a feature can be very useful since it
allows you to get at the data one clock earlier.

Why don't the Xilinx FIFOs have such a feature?
(Or am I perhaps overlooking something some crucial
drawback of show-ahead FIFOs?)

Regards,
Bertrik Sikken
Click to expand...
 
he he.. if you couldn't get data before exists .. salesmen would be out of a
job :)


"Bob" <nimby1_not_spmmm@earthlink.net> wrote in message
news:Tiabb.731$gR1.144@newsread4.news.pas.earthlink.net...
No one can get data before it exists.

Andrew


I can. You see, I've met Peter Alfke.

;-p

Bob
Click to expand...
 
Andrew Paule wrote:
I think a better way to look a this is a FWFT (first word fall through)
- standard fifo trick - you can do these in any FPGA - transparent
latch, data available tpd after clock edge.
Click to expand...
Yes, that was what I meant.
However, FIFOs from both Altera and Xilinx don't have this by default.
For Altera you need to set the "show-ahead" property on the FIFO and
Xilinx does not have this feature at all (as far as I could find).
I wonder why. Could be it the latch that makes this a problem?

Again, it looks like a very useful feature to get the data a bit
earlier (no, obviously not before it exists...). So instead of
telling the fifo "give me some data on the next clock", you already
have the data and tell the fifo "i've seen the data, on to the next".

No one can get data before
it exists.
Click to expand...
I didn't mean to imply that.

Andrew

Bertrik Sikken wrote:

Hi all,

I worked on a project using an Altera FPGA and I noticed that
their FIFOs have a 'show-ahead' feature. Currently I'm working
with an FPGA from Xilinx and I could not find a similar feature
on their FIFO's.

It seems to me such a feature can be very useful since it
allows you to get at the data one clock earlier.

Why don't the Xilinx FIFOs have such a feature?
(Or am I perhaps overlooking something some crucial
drawback of show-ahead FIFOs?)

Regards,
Bertrik Sikken
Click to expand...
 
Sounds like you have to roll your own - and yes, sales guys can get data
before it exists. You can get the flops in a Xilinx part to go
transparent - black box em as D types - then all you've got to deal with
is the cell delay and the pad I/O delay.

BTW, I've never met Peter Alfke, although I do correspond with him, but
he did invent the first fifo (Fairchild - you can look it up - name's on
the patent app), and he is one of the few factory people who seem to
have something up top. I'm not a Xilinx person (prefer other
architectures closer to ASIC types - Actel in particular), but don't get
on his case about stuff - he's in a position where he can't malign his
company - even though there are those who put out misleading data- don't
blame him, blame the guy who okayed putting the stuff out.

Andrew

Bertrik Sikken wrote:

Andrew Paule wrote:

I think a better way to look a this is a FWFT (first word fall
through) - standard fifo trick - you can do these in any FPGA -
transparent latch, data available tpd after clock edge.


Yes, that was what I meant.
However, FIFOs from both Altera and Xilinx don't have this by default.
For Altera you need to set the "show-ahead" property on the FIFO and
Xilinx does not have this feature at all (as far as I could find).
I wonder why. Could be it the latch that makes this a problem?

Again, it looks like a very useful feature to get the data a bit
earlier (no, obviously not before it exists...). So instead of
telling the fifo "give me some data on the next clock", you already
have the data and tell the fifo "i've seen the data, on to the next".

No one can get data before

it exists.


I didn't mean to imply that.

Andrew

Bertrik Sikken wrote:

Hi all,

I worked on a project using an Altera FPGA and I noticed that
their FIFOs have a 'show-ahead' feature. Currently I'm working
with an FPGA from Xilinx and I could not find a similar feature
on their FIFO's.

It seems to me such a feature can be very useful since it
allows you to get at the data one clock earlier.

Why don't the Xilinx FIFOs have such a feature?
(Or am I perhaps overlooking something some crucial
drawback of show-ahead FIFOs?)

Regards,
Bertrik Sikken
Click to expand...
 
On Sat, 20 Sep 2003 23:11:58 -0500, Andrew Paule <lsboogy@qwest.net> wrote:
I think a better way to look a this is a FWFT (first word fall through)
a standard fifo trick - you can do these in any FPGA - transparent
Latch, data available tpd after clock edge. No one can get data before
it exists.
Click to expand...
And

On Sun, 21 Sep 2003 11:30:09 -0500, Andrew Paule <lsboogy@qwest.net> wrote:
Sounds like you have to roll your own - and yes, sales guys can get data
before it exists. You can get the flops in a Xilinx part to go
transparent - black box em as D types - then all you've got to deal with
is the cell delay and the pad I/O delay.
Click to expand...
I am sorry to say that this is not a good idea. Transparent latches
in synchronous designs is a mine field for timing problems.

The correct way to implement FWFT is to make some changes to
the FIFO control state machine.

The internals of a FIFO can be thought of as comprising the following
blocks:

1) Dual port memory
2) Write logic
3) Read logic
4) State machine
5) Flags logic

Within the Read Logic portion, there is the output of the memory,
that feeds an output register.

When data is written to a fifo, it is written to the memory,
counter(s) are updated, and the Empty flag is deasserted.

When the external read side logic sees the Empty flag deasserted, it
can issue a ReadEnable, that causes the FIFO logic to read the
appropriate location of memory, load it into the output register,
and update counters and flags.

For FWFT, the difference is that logically the name of the flag
Empty is renamed to DataValid, and the state machine is changed.
Unlike normal mode where the Empty flag is telling you the status
of the internal memory (or rather, its validity), the DataValid
flag is telling you the status of the output register.

When the FIFO is empty, the DataValid flag is deasserted.
When data arrives, if the DataValid flag is deasserted, the
FIFO state machine automatically reads a word from the memory,
transfers it to the output register, and asserts DataValid.
The ReadEnable command input of a normal FIFO is also renamed
to DataTaken, and this is used by the external read side logic
to indicate that the current contens of the output register
are not needed any more. If there is no more valid data in
the memory, DataValid is deasserted, otherwise the next data
item is transfered to the output register.

The difference in the state machine logic to implement this
FWFT mode is typically less than 10 gates.

Since the output is still comming from a register clocked
by the read side clock, the static timing model is the same
for both modes, while the logic timing is as desired for
each mode.


Philip








Philip Freidin
Fliptronics
 
Hi Philip -

you're right on all cases - only thing is that you are going to be
either a half or full clock behind. FWFT Fifo's are done with
transparent latches (that's the limiter) - you have to be cautious in
use of them. I've done fifo's using the transparent latch trick that
are out running at >430MHz, in IBM SiGe (Fishkill) - but in an FPGA,
unless you pay attention to how you're routing the thing, you can have a
nightmare (One of the reasons I like Actels) - the true FWFT types have
the flags updated on the rising edge of the incoming clock and have the
synched flops (look at a Cypress or IDT design) done with the same flop
that's used for the empty flag. What you are doing is great for
avoiding problems in designs that are not well followed through, and
should be a design standard. What goes on in the newsgroups is that
some folks out there will take a quick look at things and then try to
implement them without understanding the real problems in post route
timing (especially over temperature).

Andrew

Philip Freidin wrote:

On Sat, 20 Sep 2003 23:11:58 -0500, Andrew Paule <lsboogy@qwest.net> wrote:


I think a better way to look a this is a FWFT (first word fall through)
a standard fifo trick - you can do these in any FPGA - transparent
Latch, data available tpd after clock edge. No one can get data before
it exists.



And

On Sun, 21 Sep 2003 11:30:09 -0500, Andrew Paule <lsboogy@qwest.net> wrote:


Sounds like you have to roll your own - and yes, sales guys can get data
before it exists. You can get the flops in a Xilinx part to go
transparent - black box em as D types - then all you've got to deal with
is the cell delay and the pad I/O delay.



I am sorry to say that this is not a good idea. Transparent latches
in synchronous designs is a mine field for timing problems.

The correct way to implement FWFT is to make some changes to
the FIFO control state machine.

The internals of a FIFO can be thought of as comprising the following
blocks:

1) Dual port memory
2) Write logic
3) Read logic
4) State machine
5) Flags logic

Within the Read Logic portion, there is the output of the memory,
that feeds an output register.

When data is written to a fifo, it is written to the memory,
counter(s) are updated, and the Empty flag is deasserted.

When the external read side logic sees the Empty flag deasserted, it
can issue a ReadEnable, that causes the FIFO logic to read the
appropriate location of memory, load it into the output register,
and update counters and flags.

For FWFT, the difference is that logically the name of the flag
Empty is renamed to DataValid, and the state machine is changed.
Unlike normal mode where the Empty flag is telling you the status
of the internal memory (or rather, its validity), the DataValid
flag is telling you the status of the output register.

When the FIFO is empty, the DataValid flag is deasserted.
When data arrives, if the DataValid flag is deasserted, the
FIFO state machine automatically reads a word from the memory,
transfers it to the output register, and asserts DataValid.
The ReadEnable command input of a normal FIFO is also renamed
to DataTaken, and this is used by the external read side logic
to indicate that the current contens of the output register
are not needed any more. If there is no more valid data in
the memory, DataValid is deasserted, otherwise the next data
item is transfered to the output register.

The difference in the state machine logic to implement this
FWFT mode is typically less than 10 gates.

Since the output is still comming from a register clocked
by the read side clock, the static timing model is the same
for both modes, while the logic timing is as desired for
each mode.


Philip








Philip Freidin
Fliptronics
Click to expand...
 
Bertrik, you are right in stating that the Xilinx solutions do not offer
"fall-through" as an option. We might offer that in the future.
But let's be realistic:
The only value of this option is when you write the first word into a
previously empty FIFO. Then the word appears at the output without any
Read Enable action. Once beyond this, there is no difference between
this and the conventional mode.
So it all depends whether you intend to often empty the FIFO completely.
If this is rare, the fall-through is of dubious value.

Peter Alfke
====================
Bertrik Sikken wrote:
Hi all,

I worked on a project using an Altera FPGA and I noticed that
their FIFOs have a 'show-ahead' feature. Currently I'm working
with an FPGA from Xilinx and I could not find a similar feature
on their FIFO's.

It seems to me such a feature can be very useful since it
allows you to get at the data one clock earlier.

Why don't the Xilinx FIFOs have such a feature?
(Or am I perhaps overlooking something some crucial
drawback of show-ahead FIFOs?)

Regards,
Bertrik Sikken
Click to expand...
 
Andrew Paule wrote:
Hi Philip -

you're right on all cases - only thing is that you are going to be
either a half or full clock behind. FWFT Fifo's are done with
transparent latches (that's the limiter) - you have to be cautious in
use of them. I've done fifo's using the transparent latch trick that
are out running at >430MHz, in IBM SiGe (Fishkill) - but in an FPGA,
unless you pay attention to how you're routing the thing, you can have a
nightmare (One of the reasons I like Actels) - the true FWFT types have
the flags updated on the rising edge of the incoming clock and have the
synched flops (look at a Cypress or IDT design) done with the same flop
that's used for the empty flag. What you are doing is great for
avoiding problems in designs that are not well followed through, and
should be a design standard. What goes on in the newsgroups is that
some folks out there will take a quick look at things and then try to
implement them without understanding the real problems in post route
timing (especially over temperature).
Click to expand...
Unless I am all wet, these are not true FIFOs, but are only RAM blocks
with address counters.

I am not sure you are correct about the need for transparent latches. I
don't see how you would even use a transparent latch in this application
to any advantage. I expect the RAM block is simply leaving out the
output latch on the read data. The Altera RAMs work in a way that the
output data is not available for half a clock cycle after it is written
(internal falling edge write strobe perhaps?). This may look like a
transparent latch, but it is not. In this case I don't see how you
could use a transparent latch on the output and get it to do anything
useful.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
If your external clocking is fast enough to allow use of the timing
delays inherant in the internals of your FGPA, then using a D and
running the output to a pad will allow you to get a good Tpd as the
delay - that's really all a transparent does for you in this case -
gives a one gate + one (or more pad delays). if you use the supplied
macromodels, they will do away with any use for this - roll your own
means just that, no RAM blocks. There are other architectures out there
besides Altera and Xilinx, but most of this newsgroup seems to forget
this. They all have their uses, and obviously they all have some good
points to be considered when choosing your architecture. just like the
processor people (I still like MIPs and SHARCs), but that's another
thread entirely.

Andrew

rickman wrote:

Andrew Paule wrote:


Hi Philip -

you're right on all cases - only thing is that you are going to be
either a half or full clock behind. FWFT Fifo's are done with
transparent latches (that's the limiter) - you have to be cautious in
use of them. I've done fifo's using the transparent latch trick that
are out running at >430MHz, in IBM SiGe (Fishkill) - but in an FPGA,
unless you pay attention to how you're routing the thing, you can have a
nightmare (One of the reasons I like Actels) - the true FWFT types have
the flags updated on the rising edge of the incoming clock and have the
synched flops (look at a Cypress or IDT design) done with the same flop
that's used for the empty flag. What you are doing is great for
avoiding problems in designs that are not well followed through, and
should be a design standard. What goes on in the newsgroups is that
some folks out there will take a quick look at things and then try to
implement them without understanding the real problems in post route
timing (especially over temperature).



Unless I am all wet, these are not true FIFOs, but are only RAM blocks
with address counters.

I am not sure you are correct about the need for transparent latches. I
don't see how you would even use a transparent latch in this application
to any advantage. I expect the RAM block is simply leaving out the
output latch on the read data. The Altera RAMs work in a way that the
output data is not available for half a clock cycle after it is written
(internal falling edge write strobe perhaps?). This may look like a
transparent latch, but it is not. In this case I don't see how you
could use a transparent latch on the output and get it to do anything
useful.
Click to expand...
 
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