shifting

[raghu]

consider a bit sequence 11001010. Is it possible using an operator in
verilog to shift only a part of the bit sequence i.e first 3 bits 110
<<1, kepping other bits unchanged ? The output should be 10001010.

Thanks a lot in advance.

Regards,
Raghu

 

[Jonathan Bromley]

On 10 Jul 2006 04:36:27 -0700, raghu
<raghujindia@gmail.com> wrote:

consider a bit sequence 11001010. Is it possible using an operator in
verilog to shift only a part of the bit sequence i.e first 3 bits 110
1, kepping other bits unchanged ? The output should be 10001010.

Why not?

reg [7:0] sequence;
....
sequence = 8'b11001010;
$display("Before shift: %b", sequence);
sequence[7:5] = sequence[7:5] << 1;
$display("After shift: %b", sequence);
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