Shift Register Set and Feedback

[Dimcliff]

Hi, I'm new in VHDL. I' ve wriiten a code for a 41-stage pncode. My
question is how can i set an initial value on the output of some shift
registers before the process start, and then their values will change
sequentially as usual. I can do this by putting force values using
modelsim simulator but i want to make it using an input signal just as
reset. I would be grateful if anyone could help me.

 

[Srikanth]

Dimcliff wrote:

Hi, I'm new in VHDL. I' ve wriiten a code for a 41-stage pncode. My
question is how can i set an initial value on the output of some shift
registers before the process start, and then their values will change
sequentially as usual. I can do this by putting force values using
modelsim simulator but i want to make it using an input signal just as
reset. I would be grateful if anyone could help me.

Initialize the shift register to a known value during reset.

 

[D Stanford]

Dimcliff wrote:

Hi, I'm new in VHDL. I' ve wriiten a code for a 41-stage pncode. My
question is how can i set an initial value on the output of some shift
registers before the process start, and then their values will change
sequentially as usual. I can do this by putting force values using
modelsim simulator but i want to make it using an input signal just as
reset. I would be grateful if anyone could help me.

your signal declarations can have an initial value, such as

signal my_signal : std_logic_vector(31 downto 0) := x"DEADBEEF";

 

[Dimcliff]

Ο/Η D Stanford έγραψε:

your signal declarations can have an initial value, such as

signal my_signal : std_logic_vector(31 downto 0) := x"DEADBEEF";

my registers output signal is reg. You mean that if i write

signal reg: std_logic_vector(40 downto 0) :"10000000000000000000000000000000000000000";

i can set the first flipflop on the left to '1'?
i tried something like that but i still had to force that value at the
beginning of simulation.
maybe i can't understand what you're telling me exactly.

 

[Ricardo]

Dimcliff escreveu:

signal reg: std_logic_vector(40 downto 0) :=
"10000000000000000000000000000000000000000";

i can set the first flipflop on the left to '1'?

To 1, 0, Z and all others covered by std_logic, too. Read about signal
assignement.

i tried something like that but i still had to force that value at the
beginning of simulation.

For simulation and the very first time, yes, the signal will have that
value. But as soon your reset works, it will abandon the "declaration
start value" and get the "reset value" (or better: the first assignment
value). Avoid reset is a bad pratice, IMO.

maybe i can't understand what you're telling me exactly.

Try http://tams-www.informatik.uni-hamburg.de/vhdl/ and google will
always be your friend.

 

[Thomas Stanka]

Dimcliff schrieb:

Ο/Η D Stanford έγραψε:
your signal declarations can have an initial value, such as

signal my_signal : std_logic_vector(31 downto 0) := x"DEADBEEF";


my registers output signal is reg. You mean that if i write

signal reg: std_logic_vector(40 downto 0) :> "10000000000000000000000000000000000000000";
i can set the first flipflop on the left to '1'?
i tried something like that but i still had to force that value at the
beginning of simulation.

This should do (as long as the right side contains exactly 41 values).
A better way would be := (40 => '1', others => '0'); This safes you
from reg beiing uninitilised just because of a missing 0 (or one too
much).

But this is only for simulation purpose. It is always a good idea to
use a reset for setting the register in the desired state and apply
this reset at the beginning of your simulation.

Maybe you should also think about a sychron way to set the register
during normal operation with a load function

if rising_edge(clk) then
if load='1' then
reg <= (40 => '1', others => '0');
else
reg <= lfsr_shift(reg);
......

bye Thomas

 

[Dimcliff]

Thanks to everyone who answered my question.
Now everything works fine.