shift reg 32bits

hi all,

i am would like to know if there is a simple way of coding a shift
register that loads in 32 bits and then produces 8 bits at the output
on every clock signal.

thanks,

 

[glen herrmannsfeldt]

uraniumore238@gmail.com wrote:

i am would like to know if there is a simple way of coding a shift
register that loads in 32 bits and then produces 8 bits at the output
on every clock signal.

Eight four bit shift registers is the logic you want.
That isn't hard to write in behavioral verilog
as four non-blocking assignment statements, eight
bits wide each.

-- glen

 

[General Schvantzkoph]

On Wed, 25 Mar 2009 19:43:05 -0700, uraniumore238 wrote:

hi all,

i am would like to know if there is a simple way of coding a shift
register that loads in 32 bits and then produces 8 bits at the output on
every clock signal.

thanks,
reg [31:0] shft;

always@(posedge sysclk or posedge gblreset) begin
if(gblreset) begin
shft <= 0;
end
else begin
if(ld) begin
shft <= foo;
end
else if(shf) begin
shft <= shft << 8;
end
end

 

On Mar 26, 3:54 am, General Schvantzkoph <schvantzk...@yahoo.com>
wrote:

On Wed, 25 Mar 2009 19:43:05 -0700, uraniumore238 wrote:
hi all,

i am would like to know if there is a simple way of coding a shift
register that loads in 32 bits and then produces 8 bits at the output on
every clock signal.

thanks,

reg [31:0] shft;

always@(posedge sysclk or posedge gblreset) begin
if(gblreset) begin
shft <= 0;
end
else begin
if(ld) begin
shft <= foo;
end
else if(shf) begin
shft <= shft << 8;
end
end

Let me describe what I am trying to achieve:

I am using a UART module to send a 32 BIT register to my PC through
the RS232 port on my spartan 3an. I am worried about the timing,
whether the data in the 32 BIT register will be presented to the
inport on the UART to be filled in the buffer, and if my design makes
sense.

module Top(clk, write_buffer, reset, serial_out, buffer_full,
buffer_half_full, en_16_x_baud
);

reg [7:0] data_in;
reg [31:0] data;
input wire write_buffer;
input reset;
input clk; //50 Mhz master clock
output serial_out;
output buffer_full;
output buffer_half_full;
reg [9:0] baud_count;
output reg en_16_x_baud;
reg [2:0] counter;




// Set baud rate to 96 for the UART communications
// Requires en_16_x_baud to be 153600Hz which is a single cycle pulse
every 325 cycles at 50MHz
//
// NOTE : If the highest value for baud_count exceeds 127 you will
need to adjust
// the width in the reg declaration for baud_count.
//
//--------------------------------------------------------------------------------------------------------------------------------
always @(posedge clk)
begin
if (baud_count == 324)
begin
baud_count <= 1'b0;
en_16_x_baud <= 1'b1;
end
else
begin
baud_count <= baud_count + 1;
en_16_x_baud <= 1'b0;
end
end

/*always @ (posedge clk)
begin
data<= 32'b01000101_000000000_000000000_01000101;
//counter <= counter+1;
end
*/
always @ (posedge clk, posedge reset)
begin
if(reset)
begin
data_in<=0;
counter <= 0;
data[31:0] <= 32'b0;
end

else
begin
if(write_buffer)
begin
data[31:0]<= 32'b0100010100000000000000000001000101;
end
else
begin
if(counter == 1)
data_in<=data[7:0];
else if (counter == 2)
data_in<=data[15:8];
else if (counter == 3)
data_in<=data[23:16];
else if(counter == 4)
data_in<=data[31:24];

end
counter <= counter + 1;
end


end

uart_tx uart_Tx(.data_in(data_in),
.write_buffer(write_buffer),
.reset_buffer(reset),
.en_16_x_baud(en_16_x_baud),
.serial_out(serial_out),
.buffer_full(buffer_full),
.buffer_half_full(buffer_half_full),
.clk(clk));

endmodule

 

[gabor]

On Mar 26, 2:38 pm, uraniumore...@gmail.com wrote:

On Mar 26, 3:54 am, General Schvantzkoph <schvantzk...@yahoo.com
wrote:



On Wed, 25 Mar 2009 19:43:05 -0700, uraniumore238 wrote:
hi all,

i am would like to know if there is a simple way of coding a shift
register that loads in 32 bits and then produces 8 bits at the output on
every clock signal.

thanks,

reg [31:0] shft;

always@(posedge sysclk or posedge gblreset) begin
if(gblreset) begin
 shft <= 0;
end
else begin
 if(ld) begin
  shft <= foo;
 end
 else if(shf) begin
  shft <= shft << 8;
 end
end

Let me describe what I am trying to achieve:

I am using a UART module to send a 32 BIT  register to my PC through
the RS232 port on my spartan 3an. I am worried about the timing,
whether the data in the 32 BIT register will be presented to the
inport on the UART to be filled in the buffer, and if my design makes
sense.

module Top(clk, write_buffer, reset, serial_out, buffer_full,
buffer_half_full, en_16_x_baud
    );

reg [7:0] data_in;
reg [31:0] data;
input wire write_buffer;
input reset;
input clk; //50  Mhz master clock
output serial_out;
output buffer_full;
output buffer_half_full;
reg [9:0] baud_count;
output reg en_16_x_baud;
reg [2:0] counter;

// Set baud rate to 96 for the UART communications
// Requires en_16_x_baud to be 153600Hz which is a single cycle pulse
every 325 cycles at 50MHz
//
// NOTE : If the highest value for baud_count exceeds 127 you will
need to adjust
//        the width in the reg declaration for baud_count.
//
//--------------------------------------------------------------------------------------------------------------------------------
  always @(posedge clk)
  begin
      if (baud_count == 324)
                begin
                        baud_count <= 1'b0;
                en_16_x_baud <= 1'b1;
                end
       else
                begin
                        baud_count <= baud_count + 1;
                        en_16_x_baud <= 1'b0;
        end
    end

/*always @ (posedge clk)
begin
data<= 32'b01000101_000000000_000000000_01000101;
//counter <= counter+1;
end
*/
always @ (posedge clk, posedge reset)
begin
if(reset)
begin
data_in<=0;
counter <= 0;
data[31:0] <= 32'b0;
end

else
begin
        if(write_buffer)
        begin
        data[31:0]<= 32'b0100010100000000000000000001000101;
        end
        else
        begin
                if(counter == 1)
                data_in<=data[7:0];
                else if (counter == 2)
                data_in<=data[15:8];
                else if (counter == 3)
                data_in<=data[23:16];
                else if(counter == 4)
                data_in<=data[31:24];

        end
        counter <= counter + 1;
end

end

uart_tx uart_Tx(.data_in(data_in),
                                                .write_buffer(write_buffer),
                                                .reset_buffer(reset),
                                                .en_16_x_baud(en_16_x_baud),
                                                .serial_out(serial_out),
                                                .buffer_full(buffer_full),
                                                .buffer_half_full(buffer_half_full),
                                                .clk(clk));

endmodule

A few observations:

Unless your UART has a FIFO, you need to reduce your
byte rate. Your logic counts up continuously while
write_buffer is not active. Not seeing your UART
code, maybe I missed something here, but it looks
like you probably meant to send only one byte per
write_buffer cycle?

There is nothing that would stop your counter from
continuing to count between write_buffer pulses.

data_in is only loaded on 4 of the 8 states of
counter. The first load happens when counter == 1.
So data_in will be valid starting two cycles after
write_buffer, yet you pass write_buffer directly
to the UART without delay and without stretching it
to encompass the four bytes. Again maybe you have
put logic for this in your UART, but it is not
obvious.

Regards,
Gabor

 

On Mar 27, 5:49 am, gabor <ga...@alacron.com> wrote:

On Mar 26, 2:38 pm, uraniumore...@gmail.com wrote:





On Mar 26, 3:54 am, General Schvantzkoph <schvantzk...@yahoo.com
wrote:

On Wed, 25 Mar 2009 19:43:05 -0700, uraniumore238 wrote:
hi all,

i am would like to know if there is a simple way of coding a shift
register that loads in 32 bits and then produces 8 bits at the output on
every clock signal.

thanks,

reg [31:0] shft;

always@(posedge sysclk or posedge gblreset) begin
if(gblreset) begin
 shft <= 0;
end
else begin
 if(ld) begin
  shft <= foo;
 end
 else if(shf) begin
  shft <= shft << 8;
 end
end

Let me describe what I am trying to achieve:

I am using a UART module to send a 32 BIT  register to my PC through
the RS232 port on my spartan 3an. I am worried about the timing,
whether the data in the 32 BIT register will be presented to the
inport on the UART to be filled in the buffer, and if my design makes
sense.

module Top(clk, write_buffer, reset, serial_out, buffer_full,
buffer_half_full, en_16_x_baud
    );

reg [7:0] data_in;
reg [31:0] data;
input wire write_buffer;
input reset;
input clk; //50  Mhz master clock
output serial_out;
output buffer_full;
output buffer_half_full;
reg [9:0] baud_count;
output reg en_16_x_baud;
reg [2:0] counter;

// Set baud rate to 96 for the UART communications
// Requires en_16_x_baud to be 153600Hz which is a single cycle pulse
every 325 cycles at 50MHz
//
// NOTE : If the highest value for baud_count exceeds 127 you will
need to adjust
//        the width in the reg declaration for baud_count.
//
//-------------------------------------------------------------------------­-------------------------------------------------------
  always @(posedge clk)
  begin
      if (baud_count == 324)
                begin
                        baud_count <= 1'b0;
                en_16_x_baud <= 1'b1;
                end
       else
                begin
                        baud_count <= baud_count + 1;
                        en_16_x_baud <= 1'b0;
        end
    end

/*always @ (posedge clk)
begin
data<= 32'b01000101_000000000_000000000_01000101;
//counter <= counter+1;
end
*/
always @ (posedge clk, posedge reset)
begin
if(reset)
begin
data_in<=0;
counter <= 0;
data[31:0] <= 32'b0;
end

else
begin
        if(write_buffer)
        begin
        data[31:0]<= 32'b0100010100000000000000000001000101;
        end
        else
        begin
                if(counter == 1)
                data_in<=data[7:0];
                else if (counter == 2)
                data_in<=data[15:8];
                else if (counter == 3)
                data_in<=data[23:16];
                else if(counter == 4)
                data_in<=data[31:24];

        end
        counter <= counter + 1;
end

end

uart_tx uart_Tx(.data_in(data_in),
                                                .write_buffer(write_buffer),
                                                .reset_buffer(reset),
                                                .en_16_x_baud(en_16_x_baud),
                                                .serial_out(serial_out),
                                                .buffer_full(buffer_full),
                                                .buffer_half_full(buffer_half_full),
                                                .clk(clk));

endmodule

A few observations:

Unless your UART has a FIFO, you need to reduce your
byte rate.  Your logic counts up continuously while
write_buffer is not active.  Not seeing your UART
code, maybe I missed something here, but it looks
like you probably meant to send only one byte per
write_buffer cycle?

There is nothing that would stop your counter from
continuing to count between write_buffer pulses.

data_in is only loaded on 4 of the 8 states of
counter.  The first load happens when counter == 1.
So data_in will be valid starting two cycles after
write_buffer, yet you pass write_buffer directly
to the UART without delay and without stretching it
to encompass the four bytes.  Again maybe you have
put logic for this in your UART, but it is not
obvious.

Regards,
Gabor- Hide quoted text -

- Show quoted text -

Hey Gabor,

Thanks for the advice. I have came up with another one and I am really
close to the solution. Please do critique this one for me. The UART
that I am using is from Ken Chapman UART verilog....

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:11:15 03/25/2009
// Design Name:
// Module Name: Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top(clk, reset, serial_out, buffer_full, buffer_half_full,
en_16_x_baud
);

reg [7:0] data_in;
reg [31:0] data;
reg write_buffer;
input reset;
input clk; //50 Mhz master clock
output serial_out;
output buffer_full;
output buffer_half_full;
reg [9:0] baud_count;
output reg en_16_x_baud;
reg [10:0] counter;
reg start;

// Set baud rate to 96 for the UART communications
// Requires en_16_x_baud to be 153600Hz which is a single cycle pulse
every 325 cycles at 50MHz
//
// NOTE : If the highest value for baud_count exceeds 127 you will
need to adjust
// the width in the reg declaration for baud_count.
//
//--------------------------------------------------------------------------------------------------------------------------------

always @ (posedge clk, posedge reset)
begin

if(reset)
begin
//reset all signals
data_in<=0;
counter <= 0;
data <= 32'b00000000111111110000000011111111;
baud_count <= 0;
en_16_x_baud <= 0;
start <= 1;
write_buffer <= 0;
end

else
begin

if (baud_count == 324) //enable data rate for uart_communication to
PC
begin
baud_count <= 1'b0;
en_16_x_baud <= 1'b1;
end
else
begin
baud_count <= baud_count + 1;
en_16_x_baud <= 1'b0;
end

if(start) //start uart_transfer after system reset
begin

if(counter == 0) //clock cycle 0
begin
data_in<=data[7:0]; //send data to port
write_buffer <= 1; //activate write to uart port
end

else if(counter == 1); //WAIT

else if (counter == 2) //clock cycle 1
write_buffer <= 0; //deactivate writing to the uart

else if (counter == 3)
begin
data_in<=data[15:8];
write_buffer <= 1;
end

else if (counter == 4); //WAIT

else if (counter == 5)
write_buffer <= 0;

else if (counter == 6)
begin
data_in<=data[23:16];
write_buffer <= 1;
end

else if (counter == 7); //WAIT

else if (counter == 8)
write_buffer <= 0;

else if (counter == 9)
begin
data_in<=data[31:24];
write_buffer <= 1;
end
else if (counter == 10); //WAIT

else if(counter == 11)
begin
write_buffer <= 0; //stop writing
start <= 0; //done with uart transfer
end

counter <= counter + 1;
end

end

end

//when write is asserted, the uart_tx module writes the data_in into
the 128 bits into the buffer
//and activates the buffer_full signal
uart_tx uart_Tx(.data_in(data_in),
.write_buffer(write_buffer), //write the data_in bits into the
FIFO
.reset_buffer(reset),
.en_16_x_baud(en_16_x_baud),
.serial_out(serial_out),
.buffer_full(buffer_full),
.buffer_half_full(buffer_half_full),
.clk(clk));
endmodule