shift arithmetic

[a.h e.j]

hello every one
in modelsim 10.0c i wrote >>>
i mean shift arithmetic but the modelsim doesn't know.
the second and third > are blue but the first > is black
help me how can write shift arithmetic in modelsim.
thanks

 

[Nikolaos Kavvadias]

Hi A.H.E.J.

> i mean shift arithmetic but the modelsim doesn't know.

It is not a tool matter but a language matter.

I can help you but holistically not specifically.

Can you send me a description of the entire problem?

Please note that >>> denotes right rotation in some offshoot C-like languages. In Verilog there are 2 or 3 usual ways of coding a left or right rotation.


Best regards
Nikolaos Kavvadias

Not in Τη Πέμπτη, 13 Μαρτίου 2014 6:09:51 π.μ. UTC+2, ο χρήστης a.h e.j έγραψε:

hello every one

in modelsim 10.0c i wrote

i mean shift arithmetic but the modelsim doesn't know.

the second and third > are blue but the first > is black

help me how can write shift arithmetic in modelsim.

thanks

 

[a.h e.j]

thanks Nikolaos Kavvadias
my code is:
module my(b,o0,o1);
input [4:0] b;
output [4:0] o0,o1;
wire [4:0] o0;
assign b=5'b10110;//-10
assign a=0;
assign o0=(b >>> 2);//line7: shift arithmetic
assign o1=(b >> 2); //line8: shift
endmodule

but o1=o0 i don' so >>> and >> is the same?

 

[Vince]

"a.h e.j" a écrit :

thanks Nikolaos Kavvadias
my code is:
module my(b,o0,o1);
input [4:0] b;
output [4:0] o0,o1;
wire [4:0] o0;
assign b=5'b10110;//-10
assign a=0;
assign o0=(b >>> 2);//line7: shift arithmetic
assign o1=(b >> 2); //line8: shift
endmodule

but o1=o0 i don' so >>> and >> is the same?

No it is not the same, >>> keeps the sign (ie the MSB is duplicated). >>> and
<<< are available in Verilog-2001 so make sure you compile in Verilog-2001
(refer to the manual of your simulator).

 

[Nikolaos Kavvadias]

Hi AHEJ

what are you trying to solve/achieve? I can see an attempt to the solution but not a statement of the problem.

Best regards
Nikolaos Kavvadias

PS: Your code syntactically passes through Icarus Verilog (which supports Verilog-2001).

"a.h e.j" a écrit :

thanks Nikolaos Kavvadias

my code is:

module my(b,o0,o1);

input [4:0] b;

output [4:0] o0,o1;

wire [4:0] o0;

assign b=5'b10110;//-10

assign a=0;

assign o0=(b >>> 2);//line7: shift arithmetic

assign o1=(b >> 2); //line8: shift

endmodule



but o1=o0 i don' so >>> and >> is the same?



No it is not the same, >>> keeps the sign (ie the MSB is duplicated). >>> and

are available in Verilog-2001 so make sure you compile in Verilog-2001

(refer to the manual of your simulator).

 

[GaborSzakacs]

Vince wrote:

"a.h e.j" a écrit :
thanks Nikolaos Kavvadias
my code is:
module my(b,o0,o1);
input [4:0] b;
output [4:0] o0,o1;
wire [4:0] o0;
assign b=5'b10110;//-10
assign a=0;
assign o0=(b >>> 2);//line7: shift arithmetic
assign o1=(b >> 2); //line8: shift
endmodule

but o1=o0 i don' so >>> and >> is the same?

No it is not the same, >>> keeps the sign (ie the MSB is duplicated). >>> and
are available in Verilog-2001 so make sure you compile in Verilog-2001
(refer to the manual of your simulator).

I wasn't aware that Modelsim didn't support this basic feature of
Verilog 2001 unless you have a very old version. However it was
my understanding that >>> would only operate correctly (i.e. replicate
the MSB) if the argument to be shifted was signed.

--
Gabor