Guest
hi everybody,
how i can traslate this line in C
varA = (varA<<4) + varB;
in VHDL language????
wrong exemple
varA <= (varA sll 4) + varB;
My problem is the shift "<<" i try with SHL, sll, ecc. but i cant
compile the vhdl because there is some error.
I have include librerie std_logic_arith "use
IEEE.std_logic_arith.all;" but have this error:
Operator "sll" is not defined for such operands.
Undefined type of expression.
Assignment target incompatible with right side. Expected type
"std_logic_vector".
i have tray with different type: std_logic_vector, integer, bit_vector
but i have the same result, error on compile.
pls, help me.
Jeuco
how i can traslate this line in C
varA = (varA<<4) + varB;
in VHDL language????
wrong exemple
varA <= (varA sll 4) + varB;
My problem is the shift "<<" i try with SHL, sll, ecc. but i cant
compile the vhdl because there is some error.
I have include librerie std_logic_arith "use
IEEE.std_logic_arith.all;" but have this error:
Operator "sll" is not defined for such operands.
Undefined type of expression.
Assignment target incompatible with right side. Expected type
"std_logic_vector".
i have tray with different type: std_logic_vector, integer, bit_vector
but i have the same result, error on compile.
pls, help me.
Jeuco