Shared variables and protected type

[Olaf Petzold]

Hi,

this time another question:

foo: block is

shared variable bar : std_logic;

begin
....

Modelsim/XE got error:

Shared variables must be of a protected type.

well, following http://www.csee.umbc.edu/help/VHDL/declare.html:

Note: Variables declared in subprograms and processes
must not be declared shared.
Variables declared in entities, architectures, packages and blocks
must be declared shared.
Some analysers/compilers may require shared variables
to be 'protected'.

unfortunally I didn't found any informations about making shared vars
protected in detail, wether MXE nor XST. How to do this?
I found some links about racing conditions using shared variables but
not specials/details.

Thanks and regards,
Olaf

 

[Alex Shot]

Shared variables must not be declared into blocks. Just try to define
your 'bar' into architecture or into package. It can be used into
blocks, functions and procedures.

 

[john Doef]

Olaf Petzold a écrit :

Hi,

this time another question:

foo: block is

shared variable bar : std_logic;

begin
....

Modelsim/XE got error:

Shared variables must be of a protected type.

well, following http://www.csee.umbc.edu/help/VHDL/declare.html:

Note: Variables declared in subprograms and processes
must not be declared shared.
Variables declared in entities, architectures, packages and blocks
must be declared shared.
Some analysers/compilers may require shared variables
to be 'protected'.

unfortunally I didn't found any informations about making shared vars
protected in detail, wether MXE nor XST. How to do this?
I found some links about racing conditions using shared variables but
not specials/details.
First, don't use shared variable!

Second, VHDL 2002 added protected types and requires shared variable
type to
be protected.

So either use VHDL 93 standard or create a protected type. std_logic
is not
a protected type.

Last, don't use shared variable!

JD.

 

[Olaf Petzold]

Hi,

First, don't use shared variable!

Thanks for your advice, I did found this arround the net too.

Second, VHDL 2002 added protected types and requires shared variable
type to
be protected.

So either use VHDL 93 standard or create a protected type. std_logic
is not
a protected type.

Well, for interest: How to create protected types in vhdl2002?
Modelsim/XE seems to support this, no idea aboit xst.

Thanks and regards,
Olaf

 

[john Doef]

Olaf Petzold a écrit :

Hi,
[...]
Well, for interest: How to create protected types in vhdl2002?
Search for "vhdl protected type" on the net.

Modelsim/XE seems to support this, no idea aboit xst.
Protected types are not supported for synthesis.

JD.